pass invalidate_lr through simple cache interface (#45)
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@ -1133,6 +1133,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
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val s2_req_fire = Reg(next=s1_req_fire)
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val s3_nack = Reg(next=io.cache.s2_nack)
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io.cache.invalidate_lr := io.requestor.invalidate_lr
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io.cache.req <> req_arb.io.out
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io.cache.req.bits.phys := Bool(true)
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io.cache.s1_kill := io.cache.s2_nack
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