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Revert "make sure SlowIO clock divider is initialized on reset"

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This reverts commit 546aaad8cfb03e45e068733c2b694232bcf9dcdb.
This commit is contained in:
Howard Mao 2016-06-08 13:45:30 -07:00
parent 636a46c052
commit 0969be8804
1 changed files with 2 additions and 2 deletions
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4
junctions/src/main/scala/slowio.scala
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@ -26,8 +26,8 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
}
io.divisor := (hold << 16) | divisor
val count = Reg(init = UInt(0, log2Up(divisor_max)))
val myclock = Reg(init = Bool(false))
val count = Reg{UInt(width = log2Up(divisor_max))}
val myclock = Reg{Bool()}
count := count + UInt(1)
val rising = count === (divisor >> 1)