Fix D$ for set size > page size
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dca55a2b35
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@ -71,7 +71,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val s1_req = Reg(io.cpu.req.bits)
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when (metaReadArb.io.out.valid) {
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s1_req := io.cpu.req.bits
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s1_req.addr := Cat(io.cpu.req.bits.addr >> pgIdxBits, metaReadArb.io.out.bits.idx, io.cpu.req.bits.addr(blockOffBits-1,0))
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s1_req.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaReadArb.io.out.bits.idx, io.cpu.req.bits.addr(blockOffBits-1,0))
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}
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val s1_read = isRead(s1_req.cmd)
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val s1_write = isWrite(s1_req.cmd)
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