have multiple outstanding requests in CacheFillTest
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@ -11,30 +11,33 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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val s_start :: s_prefetch :: s_retrieve :: s_finished :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val inflight = Reg(init = Bool(false))
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val active = state === s_prefetch || state === s_retrieve
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val xact_pending = Reg(init = UInt(0, tlMaxClientXacts))
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val xact_id = PriorityEncoder(~xact_pending)
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disablePorts(mem = false)
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val (xact_id, xact_flip) = Counter(io.mem.acquire.fire(), tlMaxClientXacts)
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val (req_block, round_done) = Counter(io.mem.acquire.fire(), nblocks)
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io.mem.acquire.valid := active && !inflight
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io.mem.acquire.valid := active && !xact_pending.andR
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io.mem.acquire.bits := Mux(state === s_prefetch,
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GetPrefetch(xact_id, UInt(memStartBlock) + req_block),
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GetBlock(xact_id, UInt(memStartBlock) + req_block))
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io.mem.grant.ready := inflight
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io.mem.grant.ready := xact_pending.orR
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when (io.mem.acquire.fire()) {
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inflight := Bool(true)
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def add_pending(acq: DecoupledIO[Acquire]): UInt =
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Mux(acq.fire(), UIntToOH(acq.bits.client_xact_id), UInt(0))
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def remove_pending(gnt: DecoupledIO[Grant]): UInt = {
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val last_grant = !gnt.bits.hasMultibeatData() ||
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gnt.bits.addr_beat === UInt(tlDataBeats - 1)
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~Mux(gnt.fire() && last_grant, UIntToOH(gnt.bits.client_xact_id), UInt(0))
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}
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val last_grant = !io.mem.grant.bits.hasMultibeatData() ||
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io.mem.grant.bits.addr_beat === UInt(tlDataBeats - 1)
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when (io.mem.grant.fire() && last_grant) {
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inflight := Bool(false)
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}
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xact_pending := (xact_pending |
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add_pending(io.mem.acquire)) &
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remove_pending(io.mem.grant)
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when (state === s_start) { state := s_prefetch }
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when (state === s_prefetch && round_done) { state := s_retrieve }
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