riscv/rocket-chip
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When exceptions occur in D-mode, set pc=0x808, not 0x800

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Closes #43
This commit is contained in:
Andrew Waterman 2016-06-06 20:57:22 -07:00
parent 3b0c1ed0c3
commit 4f2e2480a8
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/csr.scala
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@ -358,7 +358,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val causeIsDebugBreak = insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
val trapToDebug = Bool(usingDebug) && (causeIsDebugInt || causeIsDebugBreak || reg_debug)
val delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs))
val tvec = Mux(trapToDebug, UInt(0x800), Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec))
val debugTVec = Mux(reg_debug, UInt(0x808), UInt(0x800))
val tvec = Mux(trapToDebug, debugTVec, Mux(delegate, reg_stvec.sextTo(vaddrBitsExtended), reg_mtvec))
val epc = Mux(csr_debug, reg_dpc, Mux(Bool(p(UseVM)) && !csr_addr_priv(1), reg_sepc, reg_mepc))
io.fatc := insn_sfence_vm
io.evec := Mux(io.exception || csr_xcpt, tvec, epc)