make sure no-data voluntary releases get tracked
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ebe95fa827
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@ -113,14 +113,13 @@ class BufferedBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Param
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// A release beat can be accepted if we are idle, if its a mergeable transaction, or if its a tail beat
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io.inner.release.ready := state === s_idle || irel_can_merge || irel_same_xact
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when(irel_is_allocating) { pending_orel := io.irel().hasData() }
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when(io.inner.release.fire()) { data_buffer(io.irel().addr_beat) := io.irel().data }
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// Dispatch outer release
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outerRelease(
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coh = outer_coh.onHit(M_XWR),
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data = data_buffer(vol_ognt_counter.up.idx))
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data = data_buffer(vol_ognt_counter.up.idx),
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add_pending_send_bit = irel_is_allocating)
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quiesce() {}
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}
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@ -1045,11 +1045,16 @@ class L2WritebackUnit(val trackerId: Int)(implicit p: Parameters) extends XactTr
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// If a release didn't write back data, have to read it from data array
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readDataArray(drop_pending_bit = dropPendingBitWhenBeatHasData(io.inner.release))
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val coh = io.wb.req.bits.coh
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val needs_inner_probes = coh.inner.requiresProbesOnVoluntaryWriteback()
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val needs_outer_release = coh.outer.requiresVoluntaryWriteback()
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// Once the data is buffered we can write it back to outer memory
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outerRelease(
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coh = outer_coh,
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data = data_buffer(vol_ognt_counter.up.idx),
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add_pending_bit = addPendingBitInternal(io.data.resp))
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add_pending_data_bits = addPendingBitInternal(io.data.resp),
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add_pending_send_bit = io.wb.req.fire() && needs_outer_release)
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// Respond to the initiating transaction handler signalling completion of the writeback
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io.wb.resp.valid := state === s_busy && all_pending_done
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@ -1064,14 +1069,9 @@ class L2WritebackUnit(val trackerId: Int)(implicit p: Parameters) extends XactTr
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xact_way_en := io.wb.req.bits.way_en
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xact_addr_block := (if (cacheIdBits == 0) Cat(io.wb.req.bits.tag, io.wb.req.bits.idx)
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else Cat(io.wb.req.bits.tag, io.wb.req.bits.idx, UInt(cacheId, cacheIdBits)))
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val coh = io.wb.req.bits.coh
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val needs_inner_probes = coh.inner.requiresProbesOnVoluntaryWriteback()
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val needs_outer_release = coh.outer.requiresVoluntaryWriteback()
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when(needs_inner_probes) { initializeProbes() }
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pending_reads := Mux(needs_outer_release, ~UInt(0, width = innerDataBeats), UInt(0))
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pending_resps := UInt(0)
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pending_orel := needs_outer_release
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//pending_orel_data := UInt(0)
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pending_coh := coh
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state := Mux(needs_inner_probes, s_inner_probe, s_busy)
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}
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@ -264,18 +264,23 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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}
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trait EmitsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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val pending_orel = Reg(init=Bool(false))
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val pending_orel_send = Reg(init=Bool(false))
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val pending_orel_data = Reg(init=Bits(0, width = innerDataBeats))
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val vol_ognt_counter = Wire(new TwoWayBeatCounterStatus)
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val pending_orel = pending_orel_send || pending_orel_data.orR || vol_ognt_counter.pending
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def outerRelease(
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coh: ClientMetadata,
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buffering: Bool = Bool(true),
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data: UInt = io.irel().data,
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add_pending_bit: UInt = UInt(0)) {
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add_pending_data_bits: UInt = UInt(0),
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add_pending_send_bit: Bool = Bool(false)) {
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pending_orel_data := (pending_orel_data & dropPendingBitWhenBeatHasData(io.outer.release)) |
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addPendingBitWhenBeatHasData(io.inner.release) |
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add_pending_bit
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add_pending_data_bits
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when (add_pending_send_bit) { pending_orel_send := Bool(true) }
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when (io.outer.release.fire()) { pending_orel_send := Bool(false) }
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connectTwoWayBeatCounters(
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status = vol_ognt_counter,
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@ -290,7 +295,7 @@ trait EmitsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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pending_orel_data(vol_ognt_counter.up.idx),
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io.inner.release.valid),
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pending_orel)
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io.outer.release.bits := coh.makeVoluntaryWriteback(
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client_xact_id = UInt(0), // TODO was tracker id, but not needed?
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@ -298,9 +303,6 @@ trait EmitsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
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addr_beat = vol_ognt_counter.up.idx,
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data = data)
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when(pending_orel_data.orR) { pending_orel := Bool(true) }
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when(vol_ognt_counter.up.done) { pending_orel := Bool(false) }
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io.outer.grant.ready := state === s_busy
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scoreboard += (pending_orel, vol_ognt_counter.pending)
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