Andrew Waterman
acca0fccf5
Fix BTB not being refilled on some indirect jumps
...
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB. That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to. This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow. Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.
This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
2017-07-26 02:13:43 -07:00
Yunsup Lee
6916e5cbfb
coreplex: better names for RocketTiles in Verilog ( #890 )
2017-07-25 16:35:31 -07:00
Andrew Waterman
d43f02268b
Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend
...
Acquire before release; jump in frontend
2017-07-25 16:26:47 -07:00
Wesley W. Terpstra
c2b8b08461
tilelink: fix Fragmenter source re-use bug ( #888 )
...
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.
However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.
To solve this, we alternate an a.source bit every time D completes a txn.
2017-07-25 16:23:55 -07:00
Andrew Waterman
15878d4691
Perform some control-flow transfers within the Frontend
2017-07-25 15:19:16 -07:00
Andrew Waterman
62c4080585
Add RVC instruction patterns
2017-07-25 15:19:16 -07:00
Andrew Waterman
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
Andrew Waterman
86ccd935fc
Add method to print perf events
2017-07-25 15:19:16 -07:00
Andrew Waterman
5df8f0d1ea
Add L2 TLB miss counter
2017-07-25 15:19:16 -07:00
Andrew Waterman
3ced04b70a
Mix in trait to connect global_reset_vector
2017-07-25 15:19:16 -07:00
Yunsup Lee
c9e467a668
coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency ( #887 )
2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d
chiplink: adjust bus view to include the splitter ( #886 )
2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a
fix HasRTCModuleImp ( #885 )
2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
...
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
Megan Wachs
f2002839eb
TLFragmenter: Continuing my spot battles on requires without explanatory strings ( #882 )
2017-07-21 21:55:32 -07:00
Yunsup Lee
21954c1c73
tileink: FIFOFixer should cope with zero-latency devices
2017-07-19 19:38:27 -07:00
Howard Mao
4d784ad693
add cloneType to RegisterWriteIO and RegisterReadIO ( #874 )
2017-07-18 18:52:31 -07:00
Wesley W. Terpstra
a9c58e9d9f
diplomacy: support creating ShiftQueues as well
2017-07-18 14:57:02 -07:00
Wesley W. Terpstra
c0a3bb58e9
ShiftQueue: use Vec of Bool to support constant prop of enq.valid
2017-07-18 14:56:59 -07:00
Wesley W. Terpstra
416629b3bf
tilelink: FIFOFixer should fix no domain => domain cases ( #873 )
2017-07-17 22:32:17 -07:00
Wesley W. Terpstra
d09a985729
zero: fix attachment in multichannel case ( #870 )
2017-07-17 21:48:31 -07:00
Wesley W. Terpstra
fc75ada577
tilelink: Monitor should report line numbers of connection that failed ( #872 )
2017-07-17 21:29:14 -07:00
Howard Mao
ec57994784
fix the TLFuzzer IO ( #869 )
2017-07-17 14:59:35 -07:00
Wesley W. Terpstra
16e8709144
tilelink: it is now legal to have errors on {Release,Hint}Ack ( #864 )
2017-07-14 16:13:30 -07:00
Richard Xia
9ade7af013
Merge pull request #862 from freechipsproject/plic-max-pri-dts
...
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 17:08:21 -07:00
Richard Xia
f0481801df
Merge pull request #863 from freechipsproject/rename-offchip-interrupts-to-external-interrupts
...
Rename offchip-interrupts to external-interrupts.
2017-07-13 16:52:57 -07:00
Megan Wachs
35464782b5
PLIC: maxPriorities comes from params
2017-07-13 15:57:10 -07:00
Richard Xia
d62787357b
Rename offchip-interrupts to external-interrupts.
2017-07-13 15:56:22 -07:00
Shreesha Srinath
f2533ce825
bootrom: Adding bootrom parameters ( #857 )
...
BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.
2017-07-13 13:40:02 -07:00
Megan Wachs
f646bed3ea
PLIC: Use longer DTS name for Max Priorities.
...
I used the singular because there is really only one max priority
2017-07-13 13:37:22 -07:00
Megan Wachs
0800fd3ed9
PLIC: Add maxPri as well as ndev in DTS
2017-07-13 13:18:50 -07:00
Wesley W. Terpstra
b7f1ba3428
tilelink: FIFOFixer must support null cases ( #860 )
...
In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
2017-07-12 22:20:31 -07:00
Wesley W. Terpstra
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
Wesley W. Terpstra
09b9d33a9a
tilelink: FIFOFixer now has a policy parameter
2017-07-12 17:38:55 -07:00
Wesley W. Terpstra
b363a94480
diplomacy: add a new UNCACHEABLE RegionType
2017-07-12 16:31:50 -07:00
Wesley W. Terpstra
c8a7648169
diplomacy: only evaluate a Nexus node's map function once
2017-07-12 16:20:55 -07:00
Wesley W. Terpstra
af3976aa67
regmapper: add byte-sized RegField helper function ( #854 )
2017-07-10 21:08:02 -07:00
Megan Wachs
177ccbb663
regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was ( #855 )
2017-07-10 21:07:50 -07:00
Jim Lawson
287219da06
Merge pull request #851 from freechipsproject/chisel3clock
...
Use chisel3 Clock() method.
2017-07-10 08:33:46 -07:00
Wesley W. Terpstra
5db0e770d5
tilelink: TestSRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
702143eb33
tilelink: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
9310a33e77
apb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
Wesley W. Terpstra
28fbf1af8e
ahb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
df44b23956
axi4: SRAM can emulate incompletely populated memory
2017-07-07 21:40:39 -07:00
Wesley W. Terpstra
b2cc4b99ed
tilelink: TestSRAM reports errors on illegal access
2017-07-07 21:40:36 -07:00
Wesley W. Terpstra
e8cb6dafd3
tilelink: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
f1fb3be603
ahb: SRAM reports errors on illegal access
2017-07-07 21:15:36 -07:00
Wesley W. Terpstra
19851a7c9e
apb: SRAM reports errors on illegal access
2017-07-07 21:15:33 -07:00
Wesley W. Terpstra
025f7d890b
axi4: SRAM now reports errors on illegal address ( #852 )
2017-07-07 19:27:32 -07:00
Jim Lawson
2bf91a0558
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
...
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Megan Wachs
76a1ae667f
PLIC: (undefZero=true) Don't allow addresses to alias
...
While the spec is unclear what happens when you access unused registers in the PLIC, for user simplicity turn off register aliasing. If this becomes a performance/area issue we can revisit.
2017-07-06 17:57:08 -07:00
Andrew Waterman
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
...
L1 memory system improvements
2017-07-06 13:03:06 -07:00
Andrew Waterman
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
...
This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
Andrew Waterman
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
Andrew Waterman
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
Andrew Waterman
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
Andrew Waterman
438abc76d2
Handle TL errors in L1 I$
...
Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
Andrew Waterman
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
Andrew Waterman
e9752f76ae
Improve probe state machine
...
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
Richard Xia
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
Megan Wachs
69ab3626ca
Merge pull request #837 from freechipsproject/plic_recode
...
plic: Recode to use OH knowledge
2017-06-30 16:05:32 -07:00
Megan Wachs
8c92c50d85
plic: make assertion comment right
2017-06-30 14:25:09 -07:00
Megan Wachs
f31ae008f3
plic: Clean up comments and simplify checking
2017-06-30 14:15:26 -07:00
Megan Wachs
76f8de75e3
plic: comment tidying
2017-06-30 12:51:09 -07:00
Megan Wachs
3da26b0aa8
plic: Add some assertions to check one-hot assumptions
2017-06-30 12:32:58 -07:00
Wesley W. Terpstra
367d4aebe6
Set complete unconditionally
2017-06-30 10:15:53 -07:00
Wesley W. Terpstra
4e9f65b2ef
Simplify logic further and bugfix
...
complete was being set unconditionally
2017-06-30 10:07:39 -07:00
Megan Wachs
e8e709c941
plic: Use same recoding technique on complete as well as claim
2017-06-30 08:36:00 -07:00
Wesley W. Terpstra
3dca2bc4a3
gah
2017-06-30 01:07:29 -07:00
Wesley W. Terpstra
e43b7accf9
Fix compile error and eliminate wasteful wires
2017-06-30 01:06:02 -07:00
Megan Wachs
834bcf6b7e
PLIC: simplify some scala code
2017-06-29 19:35:15 -07:00
Megan Wachs
eae4fe1469
plic: Recode to use the knowledge that only one interrupt can be claimed at a time.
2017-06-29 19:09:57 -07:00
Wesley W. Terpstra
e3c7bb3b1f
SRAM: MemoryDevices use .reg (not .reg("mem")) ( #835 )
2017-06-29 19:07:12 -07:00
Megan Wachs
0668f13d99
debug: Fix race between resumereq and resumeack
...
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
2017-06-29 12:27:23 -07:00
Wesley W. Terpstra
5edc4546e3
rocket: add dtim and itim refs to cpus
2017-06-28 23:10:58 -07:00
Wesley W. Terpstra
7d6f8d48f2
Revert "rocket: link dtim to its cpu"
...
This reverts commit e6c2d446cc
.
2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
fbcd6f0eb2
Revert "rocket: link itim to its cpu"
...
This reverts commit 48390ed604
.
2017-06-28 23:10:57 -07:00
Henry Cook
6e5a4c687f
diplomacy: a type of connect that always disables monitors ( #828 )
2017-06-28 21:48:10 -07:00
Megan Wachs
992b480c74
Merge pull request #825 from freechipsproject/debug_wfi
...
Debug + WFI Interactions
2017-06-28 21:28:51 -07:00
Wesley W. Terpstra
66489ffa13
rom+sram: add a compatible field
2017-06-28 15:41:20 -07:00
Wesley W. Terpstra
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
Wesley W. Terpstra
02aa80a958
TLZero: include a version number
2017-06-28 15:12:46 -07:00
Wesley W. Terpstra
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
e6c2d446cc
rocket: link dtim to its cpu
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
3f6d5110cd
rocket: dtim is not a dcache
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
bca3db0866
diplomacy: add RWXC permissions also to ResourceMappings
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
5436be54ff
periphery: use SimpleBus for mmio ports
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
171e1a4c05
diplomacy: add SimpleBus to describe bridges
2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215
devices: add reg-names to most devices
2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
0bf46edb6c
diplomacy: support reg-names in DTS output
2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
852f03282f
rocket: give itim and dtim a compatible field for drivers to match
2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
6c2b770605
plic: do not output #address-cells
...
This is only needed for an interrupt-map, not an interrupt-controller.
2017-06-28 14:26:55 -07:00
Andrew Waterman
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
Andrew Waterman
8e4be40efc
Propagate wb_reg_rs2 for sfence ASID
...
This would have been a bug if we supported ASIDs.
2017-06-28 02:09:18 -07:00
Andrew Waterman
2077e4190b
Make log more sensible for long-latency operations
...
Show only one write to the destination register, not two.
2017-06-28 02:09:18 -07:00
Andrew Waterman
6f8fdff762
Basic L1 D$ ECC support
...
Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
Andrew Waterman
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
Andrew Waterman
9c78ac4d78
Add grouped method to AugmentedUInt, like Seq.grouped
2017-06-28 02:09:18 -07:00
Andrew Waterman
8989f5654c
Add swizzle method to Encoding
2017-06-28 02:09:18 -07:00
Andrew Waterman
3e04a99f61
Refactor frontend exception passing
...
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
2017-06-28 02:09:18 -07:00
Andrew Waterman
cc2f87c214
Forbid S-mode execution from user memory
...
285c81746f
2017-06-28 02:09:18 -07:00
Andrew Waterman
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
Andrew Waterman
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
Andrew Waterman
d5f80df0ae
Allow speculative I$ refill to cacheable regions
...
Backpedaling on 27b143013f
. Shaving
four cycles off of I$ miss penalty is obviously worth the HW cost.
2017-06-28 02:09:18 -07:00
Megan Wachs
3fc75c2714
debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W.
2017-06-27 17:40:58 -07:00
Megan Wachs
e1fe0f245b
debug: Don't reset debugint register, as none of the interrupt registers are.
2017-06-27 14:10:13 -07:00
Megan Wachs
136e4b6c27
debug: use consistent coding style (Reg(init ... ) vs RegInit)
2017-06-27 13:42:38 -07:00
Megan Wachs
3b9550ede3
debug: correctly declare reg_debugint
2017-06-27 13:42:38 -07:00
Megan Wachs
56839b2c62
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
2017-06-27 13:42:38 -07:00
Megan Wachs
665c2a349c
Correct Debug + WFI Interactions
...
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
Zihao Yu
c9cfe46604
rocket,Rocket: fix type mismatch ( #819 )
2017-06-27 11:22:08 -07:00
Wesley W. Terpstra
66f64a9759
tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters ( #822 )
...
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
2017-06-26 17:54:17 -07:00
Wesley W. Terpstra
8ca6c10994
tilelink2: ToAXI4 can strip off low source ID bits
...
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.
This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
2017-06-23 17:22:45 -07:00
Wesley W. Terpstra
feecfb53ed
axi4: Deinterleaver need not make a Q for an unused AXI id
2017-06-23 17:22:42 -07:00
Wesley W. Terpstra
9bea7c1c58
Merge pull request #815 from freechipsproject/reduce-others
...
Reduce others
2017-06-23 12:13:48 -07:00
Wesley W. Terpstra
2d8b2f4edd
ReduceOthers: remove constants from the balanced AND tree
2017-06-23 00:28:05 -07:00
Henry Cook
ad4b454b49
isp: passthru based on edgesOut = edgesIn ( #814 )
2017-06-22 21:23:49 -07:00
Wesley W. Terpstra
48611266fa
diplomacy: use ReduceOthers in the RegMapper
2017-06-22 19:43:47 -07:00
Wesley W. Terpstra
11d1cb02eb
util ReduceOthers produces nlogn cost ready-valid logic
2017-06-22 19:43:20 -07:00
Jack Koenig
1f137cb9ff
Merge pull request #800 from ss2783/patch-1
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GeneratorUtils: support to elaborate a RawModule
2017-06-22 12:34:41 -07:00
Colin Schmidt
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
...
* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
Henry Cook
bf431c0a53
groundtest: fix test ram width
2017-06-20 18:11:22 -07:00
Wesley W. Terpstra
2f2fe0a973
clint: don't ask for what you know (nTiles)
2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c
allow re-positionable PLIC and Clint, and change coreplex internal network names
2017-06-20 17:18:45 -07:00
Henry Cook
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
Henry Cook
6b79842e66
dcache: just left shift by untagbits to get tag
...
Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
Wesley W. Terpstra
bb309e573f
TLSplitter: special-case the case of no split necessary
2017-06-20 14:10:25 -07:00
Wesley W. Terpstra
53f030c037
TLSplitter: default policy is roundRobin
...
Track commit 274d908d98
2017-06-20 14:03:01 -07:00
Wesley W. Terpstra
1aa4f5ce33
TLSplitter: QoR improvements
...
Track commit 985d9750e6
2017-06-20 14:01:07 -07:00
Wesley W. Terpstra
f6e0dd12c8
TLSplitter: ManagerUnification is not used in Xbars
...
Track the change made in 5994714970
2017-06-20 13:58:30 -07:00
Andrew Waterman
f396b4142d
Merge pull request #806 from freechipsproject/mulh
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Improve integer mul/div
2017-06-20 13:01:16 -07:00
Colin Schmidt
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
...
* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
Andrew Waterman
a6d9884cc0
Improve integer mul/div
...
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
Richard Xia
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
Wesley W. Terpstra
93d423d202
diplomacy: optimize IdRange.contains ( #798 )
...
This should make an optimal circuit for a wider class of ranges.
2017-06-15 15:56:14 -07:00
Shreesha Srinath
4059d9417f
GeneratorUtils: support to elaborate a RawModule
2017-06-15 14:33:02 -07:00
Henry Cook
5368ea60fe
Merge pull request #757 from freechipsproject/isp-port
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Inter-System-Port
2017-06-15 13:07:19 -07:00
Wesley W. Terpstra
1f8c4ba4ca
CoreplexNetwork: don't force a buffer on the coherence manager
...
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
4a15d47061
diplomacy: BufferParams can now directly create a Queue
2017-06-14 13:47:37 -07:00
Wesley W. Terpstra
b4b165112c
PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave
...
This edge has the largest number of source bits by far. Let's just exclude it.
2017-06-13 16:59:29 -07:00
Wesley W. Terpstra
94f85e8bc8
tilelink2: TLMonitor will not create giant wires
2017-06-13 16:58:22 -07:00
Colin Schmidt
8264c0a77e
add a debug print for xbar id mappings
2017-06-13 16:58:21 -07:00
Henry Cook
9bbde9767c
rocketchip: top-level systems are now multi-IO modules
...
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
2017-06-13 13:55:45 -07:00
Henry Cook
2e8a40a23f
diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules
...
And add a MonitorBase class to be connect's return type.
2017-06-13 13:55:27 -07:00
Andrew Waterman
76af15a6ff
Fix FPU control bug for div/sqrt
...
I was examining a WB-stage control signal instead of a MEM-stage control
signal. I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
2017-06-09 15:51:06 -07:00
Andrew Waterman
8552c77972
Fix I$ reset regression FU-357
...
Can't rely on s2 TLB response, so mask using s2_valid.
2017-06-09 00:48:24 -07:00
Andrew Waterman
5a4daebbcc
minNum -> minimumNumber ( #766 )
2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6
Fix FMUL sign, again ( #789 )
2017-06-08 01:50:00 -07:00
Leway Colin
60c896b48c
Typo: is should be if ? ( #786 )
...
Typo: is should be if ?
2017-06-07 10:40:13 -07:00
Andrew Waterman
d45fc0d670
Merge pull request #785 from freechipsproject/fmul-fix
...
Fix FMUL sign of zero
2017-06-06 00:46:03 -07:00
Andrew Waterman
07ad9203ff
Fix FMUL sign of zero
2017-06-05 17:35:42 -07:00
Megan Wachs
8d2e9a8631
Merge remote-tracking branch 'origin/master' into plusarg_docstring
2017-06-05 17:23:44 -07:00
Wesley W. Terpstra
87a5665e43
axi4: only block writes if SAME master has outstanding reads ( #782 )
...
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
2017-06-05 16:54:00 -07:00
Megan Wachs
7afd5e6070
remove unnecessary whitespace. Fix grammar.
2017-06-05 16:18:57 -07:00
Megan Wachs
8440c4b1c4
plusarg_reader : Add the ability to add a documentation string.
2017-06-05 16:16:52 -07:00
solomatnikov
274d908d98
Changed TLXbar arbitration policy to roundRobin ( #781 )
2017-06-05 10:20:28 -07:00
Andrew Waterman
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
Andrew Waterman
27b143013f
Improve ITLB QoR
...
- No need to check cacheability
- Remove a gate delay from PMP path
2017-06-02 20:45:50 -07:00
Andrew Waterman
0ffb2c8baf
Simplify and improve QoR of ShiftQueue
2017-06-02 20:44:52 -07:00
Andrew Waterman
8229bdee03
Remove FP unboxing from FMA critical path
2017-06-02 20:44:52 -07:00
Andrew Waterman
7504b47bbe
Improve code quality in FP->FP and Int->FP units
2017-06-02 20:44:52 -07:00
Andrew Waterman
84c4ae775f
Improve QoR for FP->Int conversions
2017-06-02 20:44:52 -07:00
Andrew Waterman
07968df183
Refactor FP Classify
2017-06-02 20:44:52 -07:00
Andrew Waterman
6ecd58a977
Incorporate new div/sqrt unit
2017-06-02 20:44:15 -07:00
Wesley W. Terpstra
b1917e7915
coreplex: add an ISPPort trait to add cross-connect points
2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a
coreplex: unconditionally insert a Splitter between tiles and l1tol2
2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
d002cec6ac
NodeNumberer: add an adapter to map inter-chip fabrics
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
5a2a6b0386
diplomacy: add a CustomNode type that allows direct overload of methods
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
fed1f53afa
tilelink2: add a TLSplitter to be used for the ISP port
2017-06-02 20:42:17 -07:00
Wesley W. Terpstra
a4bf678954
tilelink2: fix latent Xbar truncation bug
...
This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
ce12a64f4b
tilelink2: support SplitterNodes
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
de39af7f65
tilelink2: make some Xbar methods reusable
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
0a2a93c27d
diplomacy: add the new Splitter node type
2017-06-02 20:42:16 -07:00
Wesley W. Terpstra
c695237050
diplomacy: make :=* and :*= resolution more flexible
2017-06-02 20:42:16 -07:00
edwardcwang
cdbf67be68
Add a note to wire up jtag_mfr_id ( #778 )
...
Close #774
2017-06-02 18:53:14 -07:00
Wesley W. Terpstra
e0741a2097
axi4: don't map unused masters into TL source ID space
2017-06-02 16:30:16 -07:00
Wesley W. Terpstra
80c63c0da6
rocket: include hartid in cache master names
2017-06-02 15:52:23 -07:00
Wesley W. Terpstra
d25ad10592
diplomacy: require masters to have a name
2017-06-02 15:52:20 -07:00
Wesley W. Terpstra
475ac93cdf
coreplex: print memory map using DTS, also write a JSON for it
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
ae8734da05
diplomacy: report cacheability in ResourceAddress
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
985d9750e6
tilelink2: Xbar QoR improvement
2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
9317a00896
tilelink2: ToAXI4, sort and print AXI IDs used
2017-06-02 14:27:37 -07:00
Wesley W. Terpstra
eb14329c63
tilelink2: only combine managers of the same resources
2017-06-01 15:34:43 -07:00
Wesley W. Terpstra
1f531b1593
tilelink2: improve round robin arbiter QoR
2017-06-01 15:34:40 -07:00
Wesley W. Terpstra
5994714970
diplomacy: move manager unification to meta-data only
...
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
2017-06-01 15:30:20 -07:00
Wesley W. Terpstra
0fe625c52f
diplomacy: improve PMA circuit QoR
2017-06-01 15:30:20 -07:00
Yunsup Lee
6124bf0cc2
sort entires in the printed address map ( #773 )
2017-05-31 07:45:46 -10:00
Jacob Chang
e3e77d68e6
PTW now does not require atomic memory operations, so take out the requirement ( #767 )
...
Bug fix in CSR which manifest itself when compiling a config with no extension
2017-05-26 13:11:15 -07:00
Andrew Waterman
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
Andrew Waterman
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
Henry Cook
940614625e
TLCacheCork: unsafe flag now _really_ unsafe ( #760 )
2017-05-22 19:37:11 -07:00
Wesley W. Terpstra
7f1d3c445f
Plusargs -- tilelink timeout detection from the command line ( #752 )
...
* util: PlusArg gives Chisel access to the command-line
* tilelink2: add a progress watchdog to Monitors
2017-05-18 22:49:59 -07:00
Wesley W. Terpstra
748a48f667
unittest: balance the run times of the tests
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
bea2489507
unittest: make overall test duration configurable
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
c8ba6b2feb
unittests: accept a configurable number of transactions to run
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
f6f40b1442
unit tests: all should accept timeout override
2017-05-17 14:02:59 -07:00
Wesley W. Terpstra
8c3736e0dc
tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer
2017-05-17 06:47:21 -07:00
Wesley W. Terpstra
1f2236cdb3
diplomacy: appease Jack by removing unused 1st bundles argument
2017-05-17 06:46:07 -07:00
Wesley W. Terpstra
f2d16d49c2
tilelink2: don't widen TLMonitor interface unnecessarily
2017-05-17 06:29:03 -07:00
Wesley W. Terpstra
191dad7800
diplomacy: provide connect access to edges without bundles
...
Forcing the bundles to exist early can mess up module ownership.
2017-05-17 06:29:03 -07:00
Megan Wachs
d8996ea85f
Empty commit to force travis
2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f
rocc: fix RoccExampleConfig
2017-05-16 16:44:53 -07:00
Henry Cook
a19fc2549e
tile: add tileBus xbar
2017-05-16 16:12:01 -07:00
Wesley W. Terpstra
3e2b477c0a
rational: adjust comments and add a case for N:M
2017-05-14 15:16:33 -07:00
Wesley W. Terpstra
2119df5a60
vsrc: add ClockDivider3 used to simulate unaligned clocks
2017-05-14 15:05:55 -07:00
Wesley W. Terpstra
05e7501e7a
build: include chiselName and give an example of using it ( #738 )
2017-05-12 06:25:58 -07:00
Wesley W. Terpstra
18725a05b0
DTS tweaks ( #740 )
...
* rocket: do not report 's' in isa string
* rocket: report the micro-architecture of the core
2017-05-12 05:32:57 -07:00
Henry Cook
5f3a4ada1b
diplomacy: add legalize method to AddressSet
2017-05-10 12:54:24 -07:00
Henry Cook
3af40bff8b
tilelink: better address masking for fuzzing
2017-05-10 12:54:24 -07:00
Wesley W. Terpstra
3eaa973da7
tilelink2: add earlyAck to regression
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
3e7bdcbf5e
tilelink2: Fragmenter should ignore error when not valid
2017-05-09 17:35:26 -07:00
Wesley W. Terpstra
43c9f5fe7e
tilelink2: keep earlyAck Fragmenter sources distinct
2017-05-09 17:35:22 -07:00
Andrew Waterman
3a9bbd7e58
Merge branch 'master' into vectored-stvec
2017-05-08 14:08:09 -07:00
Wesley W. Terpstra
2d8a49cc06
tilelink2: Fragmenter client must request global FIFO
2017-05-08 00:56:45 -07:00
Wesley W. Terpstra
36f4584bb1
axi4: Test AXI4-Lite in regression
2017-05-08 00:31:35 -07:00
Wesley W. Terpstra
3209e58845
axi4: SRAM support 0 userBits
2017-05-08 00:31:14 -07:00
Wesley W. Terpstra
db76ff2d86
axi4: Deinterleaver must gather R also for single ID
...
In order to guarantee that a complete R can be sent without
sinking B, the Deinterleaver must do its job even on AXI-Lite.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8fc27b0bf2
axi4: IdIndexer; a single ID does NOT imply no response interleaving
...
Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
4847c32599
tilelink: ToAXI4 - must interlock till last beat
...
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
2017-05-08 00:17:06 -07:00
Wesley W. Terpstra
8169ba6411
axi4: IdIndexer now handles 0-width IDs
2017-05-08 00:17:02 -07:00
Andrew Waterman
7eefc12705
Support vectored stvec interrupts, too
...
137812654e
2017-05-07 15:40:08 -07:00
Andrew Waterman
c6135a02df
Revert "rocket: hard-wire UXL/SXL fields to 0"
...
This reverts commit ea0714bfcb
.
We've waffled on this matter in the priv spec: 326bec83de
2017-05-07 15:23:21 -07:00
Andrew Waterman
dd1546fd69
Check PPN LSBs for superpage PTEs
...
5a32fe8782
2017-05-05 15:30:09 -07:00
Scott Johnson
1b3b228790
ITIM supports PutPartial
2017-05-04 00:57:52 -07:00
Andrew Waterman
398600d4da
Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready
2017-05-04 00:57:29 -07:00
Scott Johnson
1cc665717d
Wes fix for AXI2TL timeout when writes backed up
2017-05-04 00:54:21 -07:00
Andrew Waterman
fa6ecdf813
Fix RVC/uncacheable instruction memory performance bug
...
9c1d126965
was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
2017-05-03 17:52:06 -07:00
Henry Cook
1f1240baf1
fuzzer: allow fuzzing range to be overridden
2017-05-03 15:29:14 -07:00
Megan Wachs
f8c92d2669
Merge branch 'master' into pipeline-mmio
2017-05-03 08:37:12 -07:00
Andrew Waterman
4efcb5a139
Increase frontend decoupling ( #722 )
...
Reduce pathological RVC stalls
2017-05-03 07:54:46 -07:00
Henry Cook
05ca88fb47
Merge branch 'master' into pipeline-mmio
2017-05-03 01:59:59 -07:00
Megan Wachs
922a8ef5e0
local_interrupts: Correct off-by-1 if there is no SEIP
2017-05-02 21:55:25 -07:00
Henry Cook
4dd3345db2
Merge branch 'master' into pipeline-mmio
2017-05-02 16:23:26 -07:00
Andrew Waterman
3a1a37d41b
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
Andrew Waterman
938b089543
Remove legacy devices that use AMOALU
...
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
2017-05-02 03:05:41 -07:00
Andrew Waterman
f8151ce786
Remove subword load muxing in ScratchpadSlavePort
2017-05-02 00:14:46 -07:00
Andrew Waterman
044b6ed3f9
Improve logical ops in AMOALU
...
As with integer ALU, shave off some muxing.
2017-05-02 00:14:46 -07:00
Andrew Waterman
f49172b5bc
ScratchpadSlavePort doesn't support byte/halfword atomics
2017-05-02 00:14:46 -07:00
Wesley W. Terpstra
fe280187a1
axi4: Fragmenter cuts all input channel readys
...
AXI4 forbids any input to lead combinationally to an output.For the AXI4ToTL
direction, front-load the cuts for {AW, AR, W}.readyAXI4ToTL makes the R and
B channels irrevocable.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
3d06f01a2c
rocket: turn on early ack for ITIM
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
58a4529cc5
axi4: the last missing piece for safe FIFO ordering
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
b0b5601e8d
axi4: ToTL correct error handling
...
If there is an illegal AWADDR = 0x2 on a 32-bit bus, remapping it
to an aligned address on the error device may make the mask
inconsistent with the address + size.
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
661015a78d
axi4: switch arbiter to round robin
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
976af7a8c7
tilelink2: better width inference for {left,right}OR
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
40f18e6e43
diplomacy: optimize IdRange overlap detection
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
30f1f1e7c7
rocket: turn on early ack for DTIM
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
6ee69454c3
tilelink2: Fragmenter now supports early Ack
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
e09fa866b7
tilelink2: FIFOFixer should NOT change client request status
...
Just because some clients are not FIFO does not matter. Downstream
FIFOFixers will still present a legitimate single domain to those
client who care.
2017-05-01 22:53:41 -07:00
Scott Johnson
b040a462c9
Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
a71f708dc7
rocketchip: move the Error device to 0x3000
2017-05-01 22:53:41 -07:00
Wesley W. Terpstra
d27e1928dd
axi4: make maxFlight a per-master parameter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e1a072a644
axi4: massage test cases into shape again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
9f08c484bd
tilelink2: ToAXI4 provide FIFO order semantics
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
61a6f94196
axi4: get unit tests legal again
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
bf5cb396b9
rocketchip: relax mmio no-interleaving requirement
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
24f577c156
axi4: Deinterleaver ensures R channel ID does not change till last
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
b4188ee625
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
ca2cb033cd
rocketchip: fix uses of AXI4 Fragmenter
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
e100a943ea
axi4: simplify Fragmenter by using user bits
2017-05-01 22:53:40 -07:00
Wesley W. Terpstra
7a1d107c9e
rocketchip: include an ErrorSlave by default
2017-05-01 22:53:37 -07:00
Wesley W. Terpstra
641a4d577a
tilelink2: Error device for returning errors on demand
2017-05-01 22:53:02 -07:00
Wesley W. Terpstra
a580b17ece
axi4: IdIndexer => reduce number of needed ids
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
06efc01d96
axi4: an adapter to remove user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
f1217519f1
axi4: RegisterRouter; concurrent response illegal in AXI
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
5163ccd11f
axi4: RegisterRouter supports user bits
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
de6ea9b442
axi4: support user bits in SRAM
2017-05-01 22:53:01 -07:00
Wesley W. Terpstra
396ecacda4
AXI4: add an optional user bundle field
2017-05-01 22:53:01 -07:00
Andrew Waterman
d6e69066a5
Fix ITIM loads ( #716 )
...
An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
Andrew Waterman
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
...
@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
Megan Wachs
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
...
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
Andrew Waterman
7416f2a17e
Unbreak groundtest
2017-04-28 02:10:33 -07:00
Andrew Waterman
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00
Andrew Waterman
7c70aa593e
Minor stylistic and QoR improvements to PLIC
2017-04-27 19:35:20 -07:00
Henry Cook
3d0ed80ef6
new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels
2017-04-27 18:17:31 -07:00
Henry Cook
bdb526a9f0
coreplex: DefaultCoreplex => RocketPlex
2017-04-27 18:17:09 -07:00
Andrew Waterman
99de42d34c
Swap order of ITIM WidthWidget and Fragmenter
...
e99fa057ac
accidentally reversed them
2017-04-27 15:30:02 -07:00
Andrew Waterman
8c10caeef9
Express PMP mask generation with incrementer, not adder
...
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
2017-04-27 15:16:29 -07:00
Henry Cook
e99fa057ac
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
Andrew Waterman
b2b4725522
Fix zero-width wire issues when ITIM is disabled
2017-04-26 22:43:00 -07:00
Andrew Waterman
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
Andrew Waterman
dc753bfa95
Fix I$ elaboration when ITIM is disabled
2017-04-26 19:35:35 -07:00
Andrew Waterman
80d826b94a
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
Andrew Waterman
418879a47f
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
Andrew Waterman
ee6702e5e0
Support indexing 1-entry Seqs
...
It's a zero-width wire special case.
Closes #706 .
2017-04-26 19:35:35 -07:00
Andrew Waterman
2e23d46631
Use val instead of def in ECC calculations
...
This allows nicer-looking code to avoid generating lots of redundant nodes.
2017-04-26 19:35:35 -07:00
Megan Wachs
7ad4cc36f7
debug: Prevent writes to DATA/PROGBUF when busy
2017-04-26 11:11:21 -07:00
Henry Cook
7f5f1c7631
Merge branch 'master' into async_queue_option
2017-04-25 14:58:11 -07:00
Henry Cook
9bb0d92381
Merge branch 'master' into async_queue_option
2017-04-25 11:23:22 -07:00
Henry Cook
60d71efa36
ahb: make hreadyout fuzzing a sram parameter
2017-04-25 11:11:31 -07:00
Henry Cook
ca435c2f40
uncore: more verbose requires
2017-04-25 11:11:31 -07:00
Wesley W. Terpstra
f3ab23d068
dcache: fix stupidly wrong crossing comparison ( #703 )
2017-04-25 09:18:41 -07:00
Wesley W. Terpstra
4807ce7ced
dcache: put a flow Q to absorb back-pressure without restarting pipeline ( #701 )
...
* dcache: put a flow Q to absorb back-pressure without restarting pipeline
When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.
* dcache: provision as few stages as possible
2017-04-24 23:28:04 -07:00
Wesley W. Terpstra
9c1d126965
Allow speculative fetch to uncacheable memory if it hits in I$ ( #700 )
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@aswaterman it's in
2017-04-24 19:12:37 -07:00
Wesley W. Terpstra
11ff4dfbb9
rocket: seip (int 9) is only present if VM is enabled ( #699 )
2017-04-24 15:58:33 -07:00
Wesley W. Terpstra
d0f3004097
tilelink2: help tools save some registers in the WidthWidget ( #691 )
2017-04-24 15:13:58 -07:00
Andrew Waterman
65928dc6a0
Don't push RAS for "auipc ra, X; jalr ra, ra, Y"
2017-04-24 02:01:15 -07:00
Andrew Waterman
36a7971975
Bypass scoreboard to reduce MMIO latency
2017-04-24 02:01:15 -07:00
Andrew Waterman
845e6f7458
Filter out duplicate test suites
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I botched the refactoring in 5934c7b4b9
2017-04-24 02:01:15 -07:00
Andrew Waterman
f2d4cb8152
Update RAS speculatively from fetch stage
2017-04-24 02:01:15 -07:00