tile: add tileBus xbar

src/main/scala/rocket/Frontend.scala

@@ -183,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
   val module: HasICacheFrontendModule
   val frontend = LazyModule(new Frontend(hartid: Int))
   val hartid: Int
-  masterNode := frontend.masterNode
+  tileBus.node := frontend.masterNode
   nPTWPorts += 1
 }
 

src/main/scala/rocket/HellaCache.scala

@@ -196,7 +196,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
   def findScratchpadFromICache: Option[AddressSet]
   var nDCachePorts = 0
   val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
-  masterNode := dcache.node
+  tileBus.node := dcache.node
 }
 
 trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle {

src/main/scala/tile/BaseTile.scala

@@ -55,6 +55,8 @@ trait HasTileLinkMasterPort {
   implicit val p: Parameters
   val module: HasTileLinkMasterPortModule
   val masterNode = TLOutputNode()
+  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
+  masterNode := tileBus.node
 }
 
 trait HasTileLinkMasterPortBundle {

src/main/scala/tile/LegacyRoCC.scala

@@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
     }})))
 
   legacyRocc foreach { lr =>
-    masterNode := lr.masterNode
+    tileBus.node := lr.masterNode
     nPTWPorts += lr.nPTWPorts
     nDCachePorts += lr.nRocc
   }