riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant

This commit is contained in:
Scott Johnson 2017-04-26 16:46:57 -07:00 committed by Wesley W. Terpstra
parent a71f708dc7
commit b040a462c9
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/uncore/axi4/Test.scala
View File

@ -70,13 +70,13 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
node :=
// AXI4UserYanker()( ... once TLToAXI is updated
AXI4UserYanker()(
AXI4Deinterleaver(64)(
TLToAXI4(4)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
model.node)))))
model.node))))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@ -92,7 +92,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
{
val node = AXI4InputNode()
val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff))))
ram.node := TLFragmenter(4, 16)(xbar.node)