Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend
Acquire before release; jump in frontend
This commit is contained in:
Andrew Waterman
GitHub
commit
d43f02268b
@ -11,21 +11,20 @@ import freechips.rocketchip.tile.HasCoreParameters
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import freechips.rocketchip.util._
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case class BTBParams(
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nEntries: Int = 40,
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nEntries: Int = 32,
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nMatchBits: Int = 14,
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nPages: Int = 6,
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nRAS: Int = 2,
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nRAS: Int = 6,
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nBHT: Int = 256,
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updatesOutOfOrder: Boolean = false)
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trait HasBtbParameters extends HasCoreParameters {
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val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
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val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets)
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val entries = btbParams.nEntries
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val nRAS = btbParams.nRAS
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val updatesOutOfOrder = btbParams.updatesOutOfOrder
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val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
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@ -53,8 +52,9 @@ class RAS(nras: Int) {
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}
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class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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val history = UInt(width = log2Up(nBHT).max(1))
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val history = UInt(width = log2Up(btbParams.nBHT).max(1))
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val value = UInt(width = 2)
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val taken = Bool()
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}
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// BHT contains table of 2-bit counters and a global history register.
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@ -68,19 +68,26 @@ class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int)(implicit val p: Parameters) extends HasCoreParameters {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt, update: Bool): BHTResp = {
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def get(addr: UInt): BHTResp = {
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val res = Wire(new BHTResp)
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val index = addr(nbhtbits+1, log2Up(coreInstBytes)) ^ history
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val index = addr(nbhtbits+log2Up(coreInstBytes)-1, log2Up(coreInstBytes)) ^ history
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res.value := table(index)
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res.history := history
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val taken = res.value(0)
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when (update) { history := Cat(taken, history(nbhtbits-1,1)) }
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res.taken := res.value(0)
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res
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}
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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val index = addr(nbhtbits+1, log2Up(coreInstBytes)) ^ d.history
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def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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val index = addr(nbhtbits+log2Up(coreInstBytes)-1, log2Up(coreInstBytes)) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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}
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def resetHistory(d: BHTResp): Unit = {
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history := d.history
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}
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def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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history := Cat(taken, d.history(nbhtbits-1,1))
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}
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def advanceHistory(taken: Bool): Unit = {
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history := Cat(taken, history(nbhtbits-1,1))
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}
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private val table = Mem(nbht, UInt(width = 2))
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@ -152,7 +159,9 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val resp = Valid(new BTBResp)
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val btb_update = Valid(new BTBUpdate).flip
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val bht_update = Valid(new BHTUpdate).flip
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val bht_advance = Valid(new BTBResp).flip
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val ras_update = Valid(new RASUpdate).flip
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val ras_head = Valid(UInt(width = vaddrBits))
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}
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val idxs = Reg(Vec(entries, UInt(width=matchBits - log2Up(coreInstBytes))))
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@ -250,21 +259,34 @@ class BTB(implicit p: Parameters) extends BtbModule {
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isValid := isValid & ~idxHit
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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if (btbParams.nBHT > 0) {
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val bht = new BHT(btbParams.nBHT)
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val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR
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val res = bht.get(io.req.bits.addr, io.req.valid && io.resp.valid && isBranch)
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict)
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val res = bht.get(io.req.bits.addr)
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when (io.req.valid && io.resp.valid && isBranch) {
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bht.advanceHistory(res.taken)
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}
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when (!res.value(0) && isBranch) { io.resp.bits.taken := false }
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when (io.bht_advance.valid) {
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bht.advanceHistory(io.bht_advance.bits.bht.taken)
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}
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when (io.btb_update.valid) {
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bht.resetHistory(io.btb_update.bits.prediction.bits.bht)
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}
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when (io.bht_update.valid) {
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bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken)
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when (io.bht_update.bits.mispredict) {
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bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken)
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}
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}
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when (!res.taken && isBranch) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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}
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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if (btbParams.nRAS > 0) {
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val ras = new RAS(btbParams.nRAS)
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val doPeek = (idxHit & cfiType.map(_ === CFIType.ret).asUInt).orR
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io.ras_head.valid := !ras.isEmpty
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io.ras_head.bits := ras.peek
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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@ -90,6 +90,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0
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val tl_out_a = Wire(tl_out.a)
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tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true))
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val tl_out_c = Wire(tl_out.c)
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tl_out.c <> (if (cacheParams.acquireBeforeRelease) Queue(tl_out_c, cacheDataBeats, flow = true) else tl_out_c)
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val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
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val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))
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@ -342,7 +344,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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Wire(new TLBundleA(edge.bundle))
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}
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tl_out_a.valid := (s2_valid_cached_miss && !s2_victim_dirty) ||
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tl_out_a.valid := (s2_valid_cached_miss && (Bool(cacheParams.acquireBeforeRelease) || !s2_victim_dirty)) ||
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(s2_valid_uncached && !uncachedInFlight.asUInt.andR)
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tl_out_a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!s2_read, put, atomics)))
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@ -371,7 +373,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val grantInProgress = Reg(init=Bool(false))
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val blockProbeAfterGrantCount = Reg(init=UInt(0))
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when (blockProbeAfterGrantCount > 0) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1 }
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tl_out.d.ready := tl_out.e.ready
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val canAcceptCachedGrant = if (cacheParams.acquireBeforeRelease) release_state === s_ready else true.B
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tl_out.d.ready := Mux(grantIsCached, tl_out.e.ready && canAcceptCachedGrant, true.B)
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when (tl_out.d.fire()) {
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when (grantIsCached) {
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grantInProgress := true
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@ -406,7 +409,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// data refill
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val doRefillBeat = grantIsRefill && tl_out.d.valid // OK to ignore d.ready
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val doRefillBeat = grantIsRefill && tl_out.d.fire()
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dataArb.io.in(1).valid := doRefillBeat
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assert(dataArb.io.in(1).ready || !doRefillBeat)
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dataArb.io.in(1).bits.write := true
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@ -438,7 +441,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// Finish TileLink transaction by issuing a GrantAck
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tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached
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tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
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tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
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when (tl_out.e.fire()) { assert(tl_out.d.fire()) }
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@ -10,9 +10,13 @@ class EventSet(gate: (UInt, UInt) => Bool, events: Seq[(String, () => Bool)]) {
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def size = events.size
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def hits = events.map(_._2()).asUInt
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def check(mask: UInt) = gate(mask, hits)
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def dump() {
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for (((name, _), i) <- events.zipWithIndex)
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when (check(1.U << i)) { printf(s"Event $name\n") }
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}
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}
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class EventSets(eventSets: Seq[EventSet]) {
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class EventSets(val eventSets: Seq[EventSet]) {
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def maskEventSelector(eventSel: UInt): UInt = {
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// allow full associativity between counters and event sets (for now?)
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val setMask = (BigInt(1) << log2Ceil(eventSets.size)) - 1
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@ -81,21 +81,24 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val icache = outer.icache.module
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require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
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val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries))
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val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 4, flow = true)) }
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val fetchBytes = coreInstBytes * fetchWidth
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val tlb = Module(new TLB(log2Ceil(fetchBytes), nTLBEntries))
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val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
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val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-2)
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val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-3)
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val s1_pc = Reg(UInt(width=vaddrBitsExtended))
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val s1_speculative = Reg(Bool())
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val s2_valid = RegInit(false.B)
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val s2_pc = Reg(init=io.resetVector)
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_pc = RegInit(alignPC(io.resetVector))
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val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_tlb_resp = Reg(tlb.io.resp)
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val s2_xcpt = !s2_tlb_resp.miss && fq.io.enq.bits.xcpt.asUInt.orR
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val s2_speculative = Reg(init=Bool(false))
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val s2_partial_insn_valid = RegInit(false.B)
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val s2_partial_insn = Reg(UInt(width = coreInstBits))
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val s2_wrong_path = Reg(Bool())
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val fetchBytes = coreInstBytes * fetchWidth
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val s1_base_pc = ~(~s1_pc | (fetchBytes - 1))
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val ntpc = s1_base_pc + fetchBytes.U
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val predicted_npc = Wire(init = ntpc)
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@ -113,40 +116,15 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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else Bool(true)
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s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative))
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val s2_redirect = Wire(init = io.cpu.req.valid)
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s2_valid := false
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when (!s2_replay && !io.cpu.req.valid) {
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when (!s2_replay && !s2_redirect) {
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s2_valid := true
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s2_pc := s1_pc
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s2_speculative := s1_speculative
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s2_tlb_resp := tlb.io.resp
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}
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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when (!s2_replay) {
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btb.io.req.valid := true
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s2_btb_resp_valid := btb.io.resp.valid
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s2_btb_resp_bits := btb.io.resp.bits
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}
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when (btb.io.resp.valid && btb.io.resp.bits.taken) {
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predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
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predicted_taken := Bool(true)
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}
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// push RAS speculatively
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btb.io.ras_update.valid := btb.io.req.valid && btb.io.resp.valid && btb.io.resp.bits.cfiType.isOneOf(CFIType.call, CFIType.ret)
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val returnAddrLSBs = btb.io.resp.bits.bridx +& 1
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btb.io.ras_update.bits.returnAddr :=
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Mux(returnAddrLSBs(log2Ceil(fetchWidth)), ntpc, s1_base_pc | ((returnAddrLSBs << log2Ceil(coreInstBytes)) & (fetchBytes - 1)))
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btb.io.ras_update.bits.cfiType := btb.io.resp.bits.cfiType
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btb.io.ras_update.bits.prediction.valid := true
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}
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io.ptw <> tlb.io.ptw
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tlb.io.req.valid := !s2_replay
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tlb.io.req.bits.vaddr := s1_pc
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@ -161,12 +139,12 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_paddr := tlb.io.resp.paddr
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icache.io.s2_vaddr := s2_pc
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay
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icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
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icache.io.s2_kill := s2_valid && (s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt)
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fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
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fq.io.enq.bits.pc := s2_pc
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io.cpu.npc := ~(~Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) | (coreInstBytes-1)) // discard LSB(s)
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io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc))
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fq.io.enq.bits.data := icache.io.resp.bits.data
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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@ -176,11 +154,126 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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fq.io.enq.bits.xcpt := s2_tlb_resp
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when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true }
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update.valid := false
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btb.io.bht_advance.valid := false
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when (!s2_replay) {
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btb.io.req.valid := !s2_redirect
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s2_btb_resp_valid := btb.io.resp.valid
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s2_btb_resp_bits := btb.io.resp.bits
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}
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when (btb.io.resp.valid && btb.io.resp.bits.taken) {
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predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
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predicted_taken := Bool(true)
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}
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if (!coreParams.jumpInFrontend) {
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// push RAS speculatively
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btb.io.ras_update.valid := btb.io.req.valid && btb.io.resp.valid && btb.io.resp.bits.cfiType.isOneOf(CFIType.call, CFIType.ret)
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val returnAddrLSBs = btb.io.resp.bits.bridx +& 1
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btb.io.ras_update.bits.returnAddr :=
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Mux(returnAddrLSBs(log2Ceil(fetchWidth)), ntpc, s1_base_pc | ((returnAddrLSBs << log2Ceil(coreInstBytes)) & (fetchBytes - 1)))
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btb.io.ras_update.bits.cfiType := btb.io.resp.bits.cfiType
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btb.io.ras_update.bits.prediction.valid := true
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} else when (fq.io.enq.fire()) {
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val s2_btb_hit = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_base_pc = ~(~s2_pc | (fetchBytes-1))
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val taken_idx = Wire(UInt())
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val after_idx = Wire(UInt())
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def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
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val prevRVI = prevValid && prevBits(1,0) === 3
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val valid = fq.io.enq.bits.mask(idx) && !prevRVI
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val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
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val rvc = bits(1,0) =/= 3
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val rviBits = Cat(bits, prevBits)
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val rviBranch = rviBits(6,0) === Instructions.BEQ.value.asUInt()(6,0)
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val rviJump = rviBits(6,0) === Instructions.JAL.value.asUInt()(6,0)
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val rviJALR = rviBits(6,0) === Instructions.JALR.value.asUInt()(6,0)
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val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
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val rviCall = (rviJALR || rviJump) && rviBits(7)
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val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
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||||
val rvcJAL = Bool(xLen == 32) && bits === Instructions.C_JAL
|
||||
val rvcJump = bits === Instructions.C_J || rvcJAL
|
||||
val rvcImm = Mux(bits(14), new RVCDecoder(bits).bImm.asSInt, 0.S) | Mux(bits(14,13) === 1, new RVCDecoder(bits).jImm.asSInt, 0.S)
|
||||
val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0
|
||||
val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
|
||||
val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0
|
||||
val rvcCall = rvcJAL || rvcJALR
|
||||
val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), 0.S) | Mux(!rviBits(2), ImmGen(IMM_SB, rviBits), 0.S)
|
||||
val taken =
|
||||
prevRVI && (rviJump || rviJALR || rviBranch && s2_btb_resp_bits.bht.taken) ||
|
||||
valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && s2_btb_resp_bits.bht.taken)
|
||||
|
||||
when (!prevTaken) {
|
||||
taken_idx := idx
|
||||
after_idx := idx + 1
|
||||
btb.io.ras_update.valid := !s2_wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
|
||||
btb.io.ras_update.bits.prediction.valid := true
|
||||
btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret, CFIType.call)
|
||||
|
||||
when (!s2_btb_hit) {
|
||||
when (prevRVI && (rviJALR && !(rviReturn && btb.io.ras_head.valid)) ||
|
||||
valid && (rvcJALR || (rvcJR && !btb.io.ras_head.valid))) {
|
||||
s2_wrong_path := true
|
||||
}
|
||||
when (taken) {
|
||||
val pc = s2_base_pc | (idx*coreInstBytes)
|
||||
val npc =
|
||||
if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
|
||||
else Mux(prevRVI, pc - coreInstBytes, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
|
||||
predicted_npc := Mux(prevRVI && rviReturn || valid && rvcReturn, btb.io.ras_head.bits, npc.asUInt)
|
||||
}
|
||||
|
||||
when (prevRVI && rviBranch || valid && rvcBranch) {
|
||||
btb.io.bht_advance.valid := !s2_wrong_path && !s2_btb_resp_valid
|
||||
btb.io.bht_advance.bits := s2_btb_resp_bits
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (idx == fetchWidth-1) {
|
||||
s2_partial_insn_valid := false
|
||||
when (valid && !prevTaken && !rvc) {
|
||||
s2_partial_insn_valid := true
|
||||
s2_partial_insn := bits | 0x3
|
||||
}
|
||||
prevTaken || taken
|
||||
} else {
|
||||
scanInsns(idx + 1, valid, bits, prevTaken || taken)
|
||||
}
|
||||
}
|
||||
|
||||
btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
|
||||
|
||||
val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
|
||||
when (s2_btb_hit) {
|
||||
s2_partial_insn_valid := false
|
||||
}.otherwise {
|
||||
fq.io.enq.bits.btb.bits.bridx := taken_idx
|
||||
when (taken) {
|
||||
fq.io.enq.bits.btb.valid := true
|
||||
fq.io.enq.bits.btb.bits.taken := true
|
||||
s2_redirect := true
|
||||
}
|
||||
}
|
||||
}
|
||||
when (s2_redirect) { s2_partial_insn_valid := false }
|
||||
when (io.cpu.req.valid) { s2_wrong_path := false }
|
||||
}
|
||||
|
||||
io.cpu.resp <> fq.io.deq
|
||||
|
||||
// performance events
|
||||
io.cpu.perf.acquire := edge.done(icache.io.tl_out(0).a)
|
||||
io.cpu.perf.tlbMiss := io.ptw.req.fire()
|
||||
|
||||
def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
|
||||
}
|
||||
|
||||
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
|
||||
|
||||
@ -26,6 +26,7 @@ case class DCacheParams(
|
||||
nRPQ: Int = 16,
|
||||
nMMIOs: Int = 1,
|
||||
blockBytes: Int = 64,
|
||||
acquireBeforeRelease: Boolean = false,
|
||||
scratch: Option[BigInt] = None) extends L1CacheParams {
|
||||
|
||||
def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)
|
||||
|
||||
@ -171,6 +171,38 @@ object Instructions {
|
||||
def FMSUB_D = BitPat("b?????01??????????????????1000111")
|
||||
def FNMSUB_D = BitPat("b?????01??????????????????1001011")
|
||||
def FNMADD_D = BitPat("b?????01??????????????????1001111")
|
||||
def C_ADDI4SPN = BitPat("b????????????????000???????????00")
|
||||
def C_FLD = BitPat("b????????????????001???????????00")
|
||||
def C_LW = BitPat("b????????????????010???????????00")
|
||||
def C_FLW = BitPat("b????????????????011???????????00")
|
||||
def C_FSD = BitPat("b????????????????101???????????00")
|
||||
def C_SW = BitPat("b????????????????110???????????00")
|
||||
def C_FSW = BitPat("b????????????????111???????????00")
|
||||
def C_ADDI = BitPat("b????????????????000???????????01")
|
||||
def C_JAL = BitPat("b????????????????001???????????01")
|
||||
def C_LI = BitPat("b????????????????010???????????01")
|
||||
def C_LUI = BitPat("b????????????????011???????????01")
|
||||
def C_SRLI = BitPat("b????????????????100?00????????01")
|
||||
def C_SRAI = BitPat("b????????????????100?01????????01")
|
||||
def C_ANDI = BitPat("b????????????????100?10????????01")
|
||||
def C_SUB = BitPat("b????????????????100011???00???01")
|
||||
def C_XOR = BitPat("b????????????????100011???01???01")
|
||||
def C_OR = BitPat("b????????????????100011???10???01")
|
||||
def C_AND = BitPat("b????????????????100011???11???01")
|
||||
def C_SUBW = BitPat("b????????????????100111???00???01")
|
||||
def C_ADDW = BitPat("b????????????????100111???01???01")
|
||||
def C_J = BitPat("b????????????????101???????????01")
|
||||
def C_BEQZ = BitPat("b????????????????110???????????01")
|
||||
def C_BNEZ = BitPat("b????????????????111???????????01")
|
||||
def C_SLLI = BitPat("b????????????????000???????????10")
|
||||
def C_FLDSP = BitPat("b????????????????001???????????10")
|
||||
def C_LWSP = BitPat("b????????????????010???????????10")
|
||||
def C_FLWSP = BitPat("b????????????????011???????????10")
|
||||
def C_MV = BitPat("b????????????????1000??????????10")
|
||||
def C_ADD = BitPat("b????????????????1001??????????10")
|
||||
def C_FSDSP = BitPat("b????????????????101???????????10")
|
||||
def C_SWSP = BitPat("b????????????????110???????????10")
|
||||
def C_FSWSP = BitPat("b????????????????111???????????10")
|
||||
def CUSTOM0 = BitPat("b?????????????????000?????0001011")
|
||||
def CUSTOM0_RS1 = BitPat("b?????????????????010?????0001011")
|
||||
def CUSTOM0_RS1_RS2 = BitPat("b?????????????????011?????0001011")
|
||||
|
||||
@ -32,12 +32,17 @@ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
|
||||
val pmp = Vec(nPMPs, new PMP).asInput
|
||||
}
|
||||
|
||||
class PTWPerfEvents extends Bundle {
|
||||
val l2miss = Bool()
|
||||
}
|
||||
|
||||
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
|
||||
with HasRocketCoreParameters {
|
||||
val ptbr = new PTBR().asInput
|
||||
val sfence = Valid(new SFenceReq).flip
|
||||
val status = new MStatus().asInput
|
||||
val pmp = Vec(nPMPs, new PMP).asInput
|
||||
val perf = new PTWPerfEvents().asOutput
|
||||
}
|
||||
|
||||
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
@ -129,6 +134,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
|
||||
}
|
||||
|
||||
val l2_refill = RegNext(false.B)
|
||||
io.dpath.perf.l2miss := false
|
||||
val (l2_hit, l2_pte) = if (coreParams.nL2TLBEntries == 0) (false.B, Wire(new PTE)) else {
|
||||
class Entry extends Bundle {
|
||||
val ppn = UInt(width = ppnBits)
|
||||
@ -172,6 +178,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
|
||||
|
||||
val (s2_entry, s2_tag) = Split(s2_rdata.uncorrected, tagBits)
|
||||
val s2_hit = s2_valid && !s2_rdata.error && r_tag === s2_tag
|
||||
io.dpath.perf.l2miss := s2_valid && !(r_tag === s2_tag)
|
||||
val s2_pte = Wire(new PTE)
|
||||
s2_pte := s2_entry.asTypeOf(new Entry)
|
||||
s2_pte.g := g(r_idx)
|
||||
|
||||
@ -29,7 +29,7 @@ case class RocketCoreParams(
|
||||
mtvecWritable: Boolean = true,
|
||||
fastLoadWord: Boolean = true,
|
||||
fastLoadByte: Boolean = false,
|
||||
fastJAL: Boolean = false,
|
||||
jumpInFrontend: Boolean = true,
|
||||
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
|
||||
fpu: Option[FPUParams] = Some(FPUParams())
|
||||
) extends CoreParams {
|
||||
@ -45,7 +45,6 @@ trait HasRocketCoreParameters extends HasCoreParameters {
|
||||
|
||||
val fastLoadWord = rocketParams.fastLoadWord
|
||||
val fastLoadByte = rocketParams.fastLoadByte
|
||||
val fastJAL = rocketParams.fastJAL
|
||||
val nBreakpoints = rocketParams.nBreakpoints
|
||||
val nPMPs = rocketParams.nPMPs
|
||||
val nPerfCounters = rocketParams.nPerfCounters
|
||||
@ -106,7 +105,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
("D$ miss", () => io.dmem.perf.acquire),
|
||||
("D$ release", () => io.dmem.perf.release),
|
||||
("ITLB miss", () => io.imem.perf.tlbMiss),
|
||||
("DTLB miss", () => io.dmem.perf.tlbMiss)))))
|
||||
("DTLB miss", () => io.dmem.perf.tlbMiss),
|
||||
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
|
||||
|
||||
val decode_table = {
|
||||
(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
|
||||
@ -169,9 +169,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
val wb_reg_rs2 = Reg(Bits())
|
||||
val take_pc_wb = Wire(Bool())
|
||||
|
||||
val take_pc_id = Wire(Bool())
|
||||
val take_pc_mem_wb = take_pc_wb || take_pc_mem
|
||||
val take_pc = take_pc_mem_wb || take_pc_id
|
||||
val take_pc = take_pc_mem_wb
|
||||
|
||||
// decode stage
|
||||
val ibuf = Module(new IBuf)
|
||||
@ -194,7 +193,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
val id_rs = id_raddr.map(rf.read _)
|
||||
val ctrl_killd = Wire(Bool())
|
||||
val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt
|
||||
take_pc_id := Bool(fastJAL) && !ctrl_killd && id_ctrl.jal
|
||||
|
||||
val csr = Module(new CSRFile(perfEvents))
|
||||
val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W)
|
||||
@ -295,7 +293,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
ex_reg_xcpt := !ctrl_killd && id_xcpt
|
||||
ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
|
||||
ex_reg_btb_hit := ibuf.io.inst(0).bits.btb_hit
|
||||
when (ibuf.io.inst(0).bits.btb_hit) { ex_reg_btb_resp := ibuf.io.btb_resp }
|
||||
|
||||
when (!ctrl_killd) {
|
||||
ex_ctrl := id_ctrl
|
||||
@ -344,6 +341,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
ex_reg_cause := id_cause
|
||||
ex_reg_inst := id_inst(0)
|
||||
ex_reg_pc := ibuf.io.pc
|
||||
ex_reg_btb_resp := ibuf.io.btb_resp
|
||||
}
|
||||
|
||||
// replay inst in ex stage?
|
||||
@ -366,15 +364,17 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
val mem_br_taken = mem_reg_wdata(0)
|
||||
val mem_br_target = mem_reg_pc.asSInt +
|
||||
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
|
||||
Mux(Bool(!fastJAL) && mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
|
||||
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
|
||||
Mux(mem_reg_rvc, SInt(2), SInt(4))))
|
||||
val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & SInt(-2)).asUInt
|
||||
val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid, mem_npc =/= ibuf.io.pc, Bool(true)))
|
||||
val mem_wrong_npc =
|
||||
Mux(ex_pc_valid, mem_npc =/= ex_reg_pc,
|
||||
Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, Bool(true)))
|
||||
val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence
|
||||
val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt
|
||||
val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
|
||||
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || (Bool(!fastJAL) && mem_ctrl.jal)
|
||||
val mem_direction_misprediction = mem_reg_btb_hit && mem_ctrl.branch && mem_br_taken =/= mem_reg_btb_resp.taken
|
||||
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
|
||||
val mem_direction_misprediction = (Bool(coreParams.jumpInFrontend) || mem_reg_btb_hit) && mem_ctrl.branch && mem_br_taken =/= mem_reg_btb_resp.taken
|
||||
val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken
|
||||
take_pc_mem := mem_reg_valid && (mem_misprediction || mem_reg_sfence || (mem_ctrl.jalr && csr.io.status.debug))
|
||||
|
||||
@ -390,7 +390,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
|
||||
mem_reg_sfence := ex_sfence
|
||||
mem_reg_btb_hit := ex_reg_btb_hit
|
||||
when (ex_reg_btb_hit) { mem_reg_btb_resp := ex_reg_btb_resp }
|
||||
mem_reg_btb_resp := ex_reg_btb_resp
|
||||
mem_reg_flush_pipe := ex_reg_flush_pipe
|
||||
mem_reg_slow_bypass := ex_slow_bypass
|
||||
|
||||
@ -582,8 +582,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
io.imem.req.bits.pc :=
|
||||
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
|
||||
Mux(replay_wb || wb_reg_flush_pipe, wb_npc, // replay or flush
|
||||
Mux(take_pc_mem || Bool(!fastJAL), mem_npc, // branch misprediction
|
||||
id_npc))) // JAL
|
||||
mem_npc)) // branch misprediction
|
||||
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
|
||||
io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence
|
||||
io.imem.sfence.bits.rs1 := wb_ctrl.mem_type(0)
|
||||
@ -594,7 +593,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
|
||||
|
||||
ibuf.io.inst(0).ready := !ctrl_stalld || csr.io.interrupt
|
||||
|
||||
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && (((mem_cfi_taken || !mem_cfi) && mem_wrong_npc) || (Bool(fastJAL) && mem_ctrl.jal && !mem_reg_btb_hit)))
|
||||
io.imem.btb_update.valid := (mem_reg_replay && mem_reg_btb_hit) || (mem_reg_valid && !take_pc_wb && mem_misprediction)
|
||||
io.imem.btb_update.bits.isValid := !mem_reg_replay && mem_cfi
|
||||
io.imem.btb_update.bits.cfiType :=
|
||||
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,
|
||||
|
||||
@ -24,3 +24,4 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro
|
||||
with HasMasterAXI4MemPortModuleImp
|
||||
with HasMasterAXI4MMIOPortModuleImp
|
||||
with HasSlaveAXI4PortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
|
||||
@ -26,6 +26,7 @@ trait CoreParams {
|
||||
val instBits: Int
|
||||
val nLocalInterrupts: Int
|
||||
val nL2TLBEntries: Int
|
||||
val jumpInFrontend: Boolean
|
||||
}
|
||||
|
||||
trait HasCoreParameters extends HasTileParameters {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user