riscv/rocket-chip
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rocket: include hartid in cache master names

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This commit is contained in:
Wesley W. Terpstra 2017-06-02 15:29:30 -07:00
parent d25ad10592
commit 80c63c0da6
4 changed files with 12 additions and 11 deletions
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2
src/main/scala/groundtest/Tile.scala
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@ -69,7 +69,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
class GroundTestTile(implicit p: Parameters) extends LazyModule
with HasGroundTestParameters {
val slave = None
val dcacheOpt = tileParams.dcache.map { dc => HellaCache(dc.nMSHRs == 0) }
val dcacheOpt = tileParams.dcache.map { dc => HellaCache(0, dc.nMSHRs == 0) }
val ucLegacy = LazyModule(new TLLegacy)
val masterNode = TLOutputNode()

2
src/main/scala/rocket/DCache.scala
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@ -39,7 +39,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
}
class DCache(val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache()(p) {
class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache(hartid)(p) {
override lazy val module = new DCacheModule(this)
}

17
src/main/scala/rocket/HellaCache.scala
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@ -147,23 +147,23 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
/** Base classes for Diplomatic TL2 HellaCaches */
abstract class HellaCache(implicit p: Parameters) extends LazyModule {
abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModule {
private val cfg = p(TileKey).dcache.get
val firstMMIO = max(1, cfg.nMSHRs)
val node = TLClientNode(Seq(TLClientPortParameters(
clients = cfg.scratch.map { _ => Seq(
TLClientParameters(
name = s"Core xx DCache MMIO",
name = s"Core ${hartid} DCache MMIO",
sourceId = IdRange(0, cfg.nMMIOs),
requestFifo = true))
} getOrElse { Seq(
TLClientParameters(
name = s"Core xx DCache MMIO",
name = s"Core ${hartid} DCache",
sourceId = IdRange(0, firstMMIO),
supportsProbe = TransferSizes(1, cfg.blockBytes)),
TLClientParameters(
name = s"Core xx DCache",
name = s"Core ${hartid} DCache MMIO",
sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
requestFifo = true))
},
@ -189,9 +189,9 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
}
object HellaCache {
def apply(blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
if (blocking) LazyModule(new DCache(scratch))
else LazyModule(new NonBlockingDCache)
def apply(hartid: Int, blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
if (blocking) LazyModule(new DCache(hartid, scratch))
else LazyModule(new NonBlockingDCache(hartid))
}
}
@ -201,8 +201,9 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
val module: HasHellaCacheModule
implicit val p: Parameters
def findScratchpadFromICache: Option[AddressSet]
val hartid: Int
var nDCachePorts = 0
val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
val dcache = HellaCache(hartid, tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
tileBus.node := dcache.node
}

2
src/main/scala/rocket/NBDcache.scala
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@ -660,7 +660,7 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
io.write.ready := Bool(true)
}
class NonBlockingDCache(implicit p: Parameters) extends HellaCache()(p) {
class NonBlockingDCache(hartid: Int)(implicit p: Parameters) extends HellaCache(hartid)(p) {
override lazy val module = new NonBlockingDCacheModule(this)
}