diplomacy: support creating ShiftQueues as well
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@ -3,6 +3,7 @@
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package freechips.rocketchip.diplomacy
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import Chisel._
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import freechips.rocketchip.util.ShiftQueue
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/** Options for memory regions */
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object RegionType {
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@ -267,6 +268,13 @@ case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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def apply[T <: Data](x: DecoupledIO[T]) =
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if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
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else x
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def sq[T <: Data](x: DecoupledIO[T]) =
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if (!isDefined) x else {
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val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
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sq.io.enq <> x
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sq.io.deq
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}
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}
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object BufferParams
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