riscv/rocket-chip
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rocket: hard-wire UXL/SXL fields to 0

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a2a3346e73
This commit is contained in:
Andrew Waterman 2017-03-26 21:56:35 -07:00
parent 5b339b6bbd
commit ea0714bfcb
1 changed files with 2 additions and 7 deletions
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9
src/main/scala/rocket/CSR.scala
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@ -21,9 +21,7 @@ class MStatus extends Bundle {
val dprv = UInt(width = PRV.SZ) // effective privilege for data accesses
val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
val sd = Bool()
val zero2 = UInt(width = 27)
val sxl = UInt(width = 2)
val uxl = UInt(width = 2)
val zero2 = UInt(width = 31)
val sd_rv32 = Bool()
val zero1 = UInt(width = 8)
val tsr = Bool()
@ -363,7 +361,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val read_sip = read_mip & reg_mideleg
val read_sstatus = Wire(init = 0.U.asTypeOf(new MStatus))
read_sstatus.sd := io.status.sd
read_sstatus.uxl := io.status.uxl
read_sstatus.sd_rv32 := io.status.sd_rv32
read_sstatus.mxr := io.status.mxr
read_sstatus.sum := io.status.sum
@ -465,8 +462,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.status.sd := io.status.fs.andR || io.status.xs.andR
io.status.debug := reg_debug
io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0)
io.status.sxl := (if (usingVM) log2Ceil(xLen) - 4 else 0)
io.status.dprv := Reg(next = Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv))
if (xLen == 32)
io.status.sd_rv32 := io.status.sd
@ -570,7 +565,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
if (usingRoCC) reg_mstatus.xs := Fill(2, new_mstatus.xs.orR)
}
when (decoded_addr(CSRs.misa)) {
val mask = UInt(isaStringToMask(isaMaskString))
val mask = UInt(isaStringToMask(isaMaskString), xLen)
val f = wdata('f' - 'a')
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
}