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unittest: balance the run times of the tests

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This commit is contained in:
Wesley W. Terpstra 2017-05-17 14:02:14 -07:00
parent bea2489507
commit 748a48f667
1 changed files with 25 additions and 25 deletions
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50
src/main/scala/unittest/Configs.scala
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@ -19,15 +19,15 @@ class WithUncoreUnitTests extends Config((site, here, up) => {
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLFuzzRAMTest( txns=5*txns, timeout=timeout)),
Module(new uncore.ahb.AHBBridgeTest(true, txns=5*txns, timeout=timeout)),
Module(new uncore.ahb.AHBNativeTest(true, txns=5*txns, timeout=timeout)),
Module(new uncore.ahb.AHBNativeTest(false, txns=5*txns, timeout=timeout)),
Module(new uncore.apb.APBBridgeTest(true, txns=5*txns, timeout=timeout)),
Module(new uncore.apb.APBBridgeTest(false, txns=5*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4LiteFuzzRAMTest( txns=5*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4FullFuzzRAMTest( txns=5*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4BridgeTest( txns=5*txns, timeout=timeout))) }
Module(new uncore.tilelink2.TLFuzzRAMTest( txns=3*txns, timeout=timeout)),
Module(new uncore.ahb.AHBBridgeTest(true, txns=8*txns, timeout=timeout)),
Module(new uncore.ahb.AHBNativeTest(true, txns=6*txns, timeout=timeout)),
Module(new uncore.ahb.AHBNativeTest(false, txns=6*txns, timeout=timeout)),
Module(new uncore.apb.APBBridgeTest(true, txns=6*txns, timeout=timeout)),
Module(new uncore.apb.APBBridgeTest(false, txns=6*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4FullFuzzRAMTest( txns=3*txns, timeout=timeout)),
Module(new uncore.axi4.AXI4BridgeTest( txns=3*txns, timeout=timeout))) }
})
class WithTLSimpleUnitTests extends Config((site, here, up) => {
@ -36,15 +36,15 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLRAMSimpleTest(1, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMSimpleTest(4, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMSimpleTest(16, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMZeroDelayTest(4, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRR0Test( txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRR1Test( txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMRationalCrossingTest(txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMAsyncCrossingTest( txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMAtomicAutomataTest( txns=5*txns, timeout=timeout)) ) }
Module(new uncore.tilelink2.TLRAMSimpleTest(1, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMSimpleTest(4, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMSimpleTest(16, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMZeroDelayTest(4, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRR0Test( txns= 3*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRR1Test( txns= 3*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMAsyncCrossingTest( txns= 5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMAtomicAutomataTest( txns=10*txns, timeout=timeout)) ) }
})
class WithTLWidthUnitTests extends Config((site, here, up) => {
@ -53,12 +53,12 @@ class WithTLWidthUnitTests extends Config((site, here, up) => {
val txns = 100 * site(TestDurationMultiplier)
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4, txns=5*txns, timeout=timeout)) ) }
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16, txns=15*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1, txns= 1*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4, txns= 5*txns, timeout=timeout)) ) }
})
class WithTLXbarUnitTests extends Config((site, here, up) => {
@ -70,7 +70,7 @@ class WithTLXbarUnitTests extends Config((site, here, up) => {
Module(new uncore.tilelink2.TLRAMXbarTest(1, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMXbarTest(2, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLRAMXbarTest(8, txns=5*txns, timeout=timeout)),
Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4, txns=5*txns, timeout=timeout)) ) }
Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) }
})
class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)