riscv/rocket-chip
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rocket: do not require FIFO order for memory-like regions

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This commit is contained in:
Wesley W. Terpstra 2017-07-12 16:20:22 -07:00
parent 09b9d33a9a
commit 4eface8a9e
2 changed files with 7 additions and 5 deletions
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6
src/main/scala/coreplex/RocketTiles.scala
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@ -61,7 +61,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
case SynchronousCrossing(params) => {
val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
val buffer = LazyModule(new TLBuffer(params))
val fixer = LazyModule(new TLFIFOFixer)
val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
buffer.node :=* wrapper.masterNode
fixer.node :=* buffer.node
tile_splitter.node :=* fixer.node
@ -79,7 +79,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = LazyModule(new TLAsyncCrossingSource(sync))
val fixer = LazyModule(new TLFIFOFixer)
val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
sink.node :=* wrapper.masterNode
fixer.node :=* sink.node
tile_splitter.node :=* fixer.node
@ -99,7 +99,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink(direction))
val source = LazyModule(new TLRationalCrossingSource)
val fixer = LazyModule(new TLFIFOFixer)
val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
sink.node :=* wrapper.masterNode
fixer.node :=* sink.node
tile_splitter.node :=* fixer.node

6
src/main/scala/rocket/HellaCache.scala
View File

@ -183,8 +183,10 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
val io = new HellaCacheBundle(outer)
val tl_out = io.mem(0)
// IOMSHRs must be FIFO
edge.manager.requireFifo()
// IOMSHRs must be FIFO for all regions with effects
edge.manager.managers.foreach { m =>
require (m.fifoId == Some(0) || !TLFIFOFixer.allUncacheable(m))
}
}
object HellaCache {