riscv/rocket-chip
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coreplex: unconditionally insert a Splitter between tiles and l1tol2

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This commit is contained in:
Wesley W. Terpstra 2017-05-19 17:55:57 -07:00
parent d002cec6ac
commit 81d372137a
3 changed files with 10 additions and 7 deletions
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5
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -13,6 +13,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val module: CoreplexNetworkModule
def bindingTree: ResourceMap
val tile_splitter = LazyModule(new TLSplitter)
val l1tol2 = LazyModule(new TLXbar)
val l1tol2_beatBytes = l1tol2Config.beatBytes
val l1tol2_lineBytes = p(CacheBlockBytes)
@ -34,6 +36,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
private val l2in_buffer = LazyModule(new TLBuffer)
private val l2in_fifo = LazyModule(new TLFIFOFixer)
l1tol2.node :=* l2in_fifo.node
l1tol2.node :=* tile_splitter.node
l2in_fifo.node :=* l2in_buffer.node
l2in_buffer.node :=* l2in
@ -83,7 +86,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
}
// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
lazy val topManagers = Some(ManagerUnification(l1tol2.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)))
lazy val topManagers = Some(ManagerUnification(tile_splitter.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)))
ResourceBinding {
val managers = topManagers.get
val max = managers.flatMap(_.address).map(_.max).max

8
src/main/scala/coreplex/RocketTiles.scala
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@ -36,7 +36,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val pWithExtra = p.alterPartial {
case TileKey => c
case BuildRoCC => c.rocc
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
}
val asyncIntXbar = LazyModule(new IntXbar)
@ -64,7 +64,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val fixer = LazyModule(new TLFIFOFixer)
buffer.node :=* wrapper.masterNode
fixer.node :=* buffer.node
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
wrapper.slaveNode :*= cbus.node
wrapper.asyncIntNode := asyncIntXbar.intnode
wrapper.periphIntNode := periphIntXbar.intnode
@ -82,7 +82,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode
fixer.node :=* sink.node
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
wrapper.slaveNode :*= source.node
wrapper.asyncIntNode := asyncIntXbar.intnode
wrapper.periphIntNode := periphIntXbar.intnode
@ -102,7 +102,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode
fixer.node :=* sink.node
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
wrapper.slaveNode :*= source.node
wrapper.asyncIntNode := asyncIntXbar.intnode
wrapper.periphIntNode := periphIntXbar.intnode

4
src/main/scala/groundtest/Coreplex.scala
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@ -24,7 +24,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
case TileId => i
case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
case AmoAluOperandBits => site(XLen)
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
case TLId => "L1toL2"
case TLKey("L1toL2") =>
TileLinkParameters(
@ -41,7 +41,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
}
val fixer = LazyModule(new TLFIFOFixer)
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
tiles.foreach { fixer.node :=* _.masterNode }
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))