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tilelink: TestSRAM can emulate incompletely populated memory

This commit is contained in:
Wesley W. Terpstra 2017-07-07 21:13:48 -07:00
parent 702143eb33
commit 5db0e770d5
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/devices/tilelink/TestRAM.scala
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@ -9,13 +9,13 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
// Do not use this for synthesis! Only for simulation.
class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule
{
val device = new MemoryDevice
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),
address = List(address) ++ errors,
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = executable,