Size hartid field with NTiles, not XLen

src/main/scala/rocket/CSR.scala

@@ -153,7 +153,7 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
 class CSRFileIO(implicit p: Parameters) extends CoreBundle
     with HasRocketCoreParameters {
   val interrupts = new TileInterrupts().asInput
-  val hartid = UInt(INPUT, xLen)
+  val hartid = UInt(INPUT, hartIdLen)
   val rw = new Bundle {
     val addr = UInt(INPUT, CSR.ADDRSZ)
     val cmd = Bits(INPUT, CSR.SZ)

src/main/scala/rocket/Frontend.scala

@@ -61,7 +61,7 @@ class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
   val tl_out = outer.node.bundleOut
   val tl_in = outer.slaveNode.map(_.bundleIn)
   val resetVector = UInt(INPUT, vaddrBitsExtended)
-  val hartid = UInt(INPUT, p(XLen))
+  val hartid = UInt(INPUT, hartIdLen)
 }
 
 class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)

src/main/scala/rocket/HellaCache.scala

@@ -158,9 +158,8 @@ abstract class HellaCache(implicit p: Parameters) extends LazyModule {
   val module: HellaCacheModule
 }
 
-class HellaCacheBundle(outer: HellaCache) extends Bundle {
-  implicit val p = outer.p
-  val hartid = UInt(INPUT, p(XLen))
+class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBundle()(p) {
+  val hartid = UInt(INPUT, hartIdLen)
   val cpu = (new HellaCacheIO).flip
   val ptw = new TLBPTWIO()
   val mem = outer.node.bundleOut

src/main/scala/rocket/ICache.scala

@@ -55,7 +55,7 @@ class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends
 }
 
 class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
-  val hartid = UInt(INPUT, p(XLen))
+  val hartid = UInt(INPUT, hartIdLen)
   val req = Decoupled(new ICacheReq).flip
   val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
   val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req

src/main/scala/rocket/Tile.scala

@@ -176,11 +176,11 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
   xing.intnode := intNode
 
   lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
+    val io = new CoreBundle {
       val master = masterNode.bundleOut
       val slave = slaveNode.bundleIn
       val interrupts = intNode.bundleIn
-      val hartid = UInt(INPUT, p(XLen))
+      val hartid = UInt(INPUT, hartIdLen)
       val resetVector = UInt(INPUT, p(XLen))
     }
     // signals that do not change:
@@ -208,11 +208,11 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
   xing.intnode := intNode
 
   lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
+    val io = new CoreBundle {
       val master = masterNode.bundleOut
       val slave = slaveNode.bundleIn
       val interrupts = intNode.bundleIn
-      val hartid = UInt(INPUT, p(XLen))
+      val hartid = UInt(INPUT, hartIdLen)
       val resetVector = UInt(INPUT, p(XLen))
     }
     // signals that do not change:
@@ -244,11 +244,11 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet
   xing.intnode := intNode
 
   lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
+    val io = new CoreBundle {
       val master = masterNode.bundleOut
       val slave = slaveNode.bundleIn
       val interrupts = intNode.bundleIn
-      val hartid = UInt(INPUT, p(XLen))
+      val hartid = UInt(INPUT, hartIdLen)
       val resetVector = UInt(INPUT, p(XLen))
     }
     // signals that do not change:

src/main/scala/tile/BaseTile.scala

@@ -31,6 +31,7 @@ trait HasTileParameters {
   val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
   val usingPTW = usingVM
   val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
+  val hartIdLen = log2Up(p(uncore.devices.NTiles))
 
   def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
 }
@@ -71,9 +72,10 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends
 }
 
 class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
+    with HasTileParameters
     with HasTileLinkMasterPortBundle
     with HasExternalInterruptsBundle {
-  val hartid = UInt(INPUT, p(XLen))
+  val hartid = UInt(INPUT, hartIdLen)
   val resetVector = UInt(INPUT, p(XLen))
 }
 

src/main/scala/tile/Core.scala

@@ -75,11 +75,11 @@ abstract class CoreModule(implicit val p: Parameters) extends Module
 abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
   with HasCoreParameters
 
-trait HasCoreIO {
+trait HasCoreIO extends HasTileParameters {
   implicit val p: Parameters
   val io = new Bundle {
     val interrupts = new TileInterrupts().asInput
-    val hartid = UInt(INPUT, p(XLen))
+    val hartid = UInt(INPUT, hartIdLen)
     val imem  = new FrontendIO()(p)
     val dmem = new HellaCacheIO()(p)
     val ptw = new DatapathPTWIO().flip