axi4: ToTL supporting pipelined MMIO
This commit is contained in:
Wesley W. Terpstra
parent
ca2cb033cd
commit
b4188ee625
@ -32,7 +32,9 @@ trait CoreplexNetwork extends HasCoreplexParameters {
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// Allows a variable number of inputs from outside to the Xbar
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private val l2in_buffer = LazyModule(new TLBuffer)
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l1tol2.node :=* l2in_buffer.node
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private val l2in_fifo = LazyModule(new TLFIFOFixer)
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l1tol2.node :=* l2in_fifo.node
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l2in_fifo.node :=* l2in_buffer.node
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l2in_buffer.node :=* l2in
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private val l2out_buffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none))
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@ -10,24 +10,27 @@ import uncore.tilelink2._
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case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
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dFn = { case AXI4MasterPortParameters(masters, userBits, maxFlight) =>
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require (userBits == 0, "AXI4 user bits cannot be transported by TL")
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require (maxFlight > 0, "AXI4 must include a maximum transactions per ID to convert to TL")
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TLClientPortParameters(clients = masters.map { m =>
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TLClientParameters(
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sourceId = IdRange((maxFlight * m.id.start) << 1, (maxFlight * m.id.end) << 1), // R+W ids are distinct
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nodePath = m.nodePath)
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})
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TLClientPortParameters(
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clients = masters.flatMap { m =>
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for (id <- m.id.start until m.id.end)
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yield TLClientParameters(
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sourceId = IdRange(id * maxFlight*2, (id+1) * maxFlight*2), // R+W ids are distinct
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nodePath = m.nodePath,
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requestFifo = true)
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})
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},
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uFn = { mp => AXI4SlavePortParameters(
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slaves = mp.managers.map { m =>
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val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
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AXI4SlaveParameters(
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address = m.address,
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resources = m.resources,
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regionType = m.regionType,
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executable = m.executable,
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nodePath = m.nodePath,
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supportsWrite = m.supportsPutPartial,
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supportsRead = m.supportsGet,
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supportsWrite = m.supportsPutPartial.intersect(maxXfer),
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supportsRead = m.supportsGet.intersect(maxXfer),
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interleavedId = Some(0))}, // TL2 never interleaves D beats
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beatBytes = mp.beatBytes,
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minLatency = mp.minLatency)
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@ -47,58 +50,64 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
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val numIds = edgeIn.master.endId
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val beatBytes = edgeOut.manager.beatBytes
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val countBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1
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val maxFlight = edgeIn.master.maxFlight
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val addedBits = log2Ceil(maxFlight) + 1
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require (edgeIn.master.userBits == 0, "AXI4 user bits cannot be transported by TL")
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require (edgeIn.master.masters(0).aligned)
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edgeOut.manager.requireFifo()
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// Look for an Error device to redirect bad requests
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val errorDevs = edgeOut.manager.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
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require (!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
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val error = errorDevs.head.address.head.base
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require (errorDevs.head.supportsPutPartial.contains(edgeOut.manager.maxTransfer),
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s"Error device supports ${errorDevs.head.supportsPutPartial} PutPartial but must support ${edgeOut.manager.maxTransfer}")
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require (errorDevs.head.supportsGet.contains(edgeOut.manager.maxTransfer),
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s"Error device supports ${errorDevs.head.supportsGet} Get but must support ${edgeOut.manager.maxTransfer}")
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val r_out = Wire(out.a)
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val r_inflight = RegInit(UInt(0, width = numIds))
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val r_block = r_inflight(in.ar.bits.id)
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val r_size1 = in.ar.bits.bytes1()
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val r_size = OH1ToUInt(r_size1)
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val r_addr = in.ar.bits.addr
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val r_ok = edgeOut.manager.supportsGetSafe(r_addr, r_size)
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val r_err_in = Wire(Decoupled(new AXI4BundleRError(in.ar.bits.params)))
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val r_err_out = Queue(r_err_in, 2)
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val r_count = RegInit(UInt(0, width = in.ar.bits.params.lenBits))
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val r_last = r_count === in.ar.bits.len
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val r_ok = edgeOut.manager.supportsGetSafe(in.ar.bits.addr, r_size)
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val r_addr = Mux(r_ok, in.ar.bits.addr, UInt(error))
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val r_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) })
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val r_id = Cat(in.ar.bits.id, r_count(in.ar.bits.id), UInt(0, width=1))
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assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, countBits)) // because aligned
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in.ar.ready := Mux(r_ok, r_out.ready, r_err_in.ready && r_last) && !r_block
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r_out.valid := in.ar.valid && !r_block && r_ok
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r_out.bits := edgeOut.Get(in.ar.bits.id << 1 | UInt(1), r_addr, r_size)._2
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r_err_in.valid := in.ar.valid && !r_block && !r_ok
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r_err_in.bits.last := r_last
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r_err_in.bits.id := in.ar.bits.id
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in.ar.ready := r_out.ready
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r_out.valid := in.ar.valid
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r_out.bits := edgeOut.Get(r_id, r_addr, r_size)._2
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when (r_err_in.fire()) { r_count := Mux(r_last, UInt(0), r_count + UInt(1)) }
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val r_sel = UIntToOH(in.ar.bits.id, numIds)
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(r_sel.toBools zip r_count) foreach { case (s, r) =>
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when (in.ar.fire() && s) { r := r + UInt(1) }
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}
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val w_out = Wire(out.a)
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val w_inflight = RegInit(UInt(0, width = numIds))
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val w_block = w_inflight(in.aw.bits.id)
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val w_size1 = in.aw.bits.bytes1()
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val w_size = OH1ToUInt(w_size1)
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val w_addr = in.aw.bits.addr
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val w_ok = edgeOut.manager.supportsPutPartialSafe(w_addr, w_size)
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val w_err_in = Wire(Decoupled(in.aw.bits.id))
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val w_err_out = Queue(w_err_in, 2)
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val w_ok = edgeOut.manager.supportsPutPartialSafe(in.aw.bits.addr, w_size)
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val w_addr = Mux(w_ok, in.aw.bits.addr, UInt(error))
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val w_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) })
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val w_id = Cat(in.aw.bits.id, w_count(in.aw.bits.id), UInt(1, width=1))
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assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, countBits)) // because aligned
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assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned
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in.aw.ready := Mux(w_ok, w_out.ready, w_err_in.ready) && in.w.valid && in.w.bits.last && !w_block
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in.w.ready := Mux(w_ok, w_out.ready, w_err_in.ready || !in.w.bits.last) && in.aw.valid && !w_block
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w_out.valid := in.aw.valid && in.w.valid && !w_block && w_ok
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w_out.bits := edgeOut.Put(in.aw.bits.id << 1, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2
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w_err_in.valid := in.aw.valid && in.w.valid && !w_block && !w_ok && in.w.bits.last
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w_err_in.bits := in.aw.bits.id
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in.aw.ready := w_out.ready && in.w.valid && in.w.bits.last
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in.w.ready := w_out.ready && in.aw.valid
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w_out.valid := in.aw.valid && in.w.valid
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w_out.bits := edgeOut.Put(w_id, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2
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val w_sel = UIntToOH(in.aw.bits.id, numIds)
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(w_sel.toBools zip w_count) foreach { case (s, r) =>
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when (in.aw.fire() && s) { r := r + UInt(1) }
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}
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TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (UInt(0), r_out), (in.aw.bits.len, w_out))
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val ok_b = Wire(in.b)
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val err_b = Wire(in.b)
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val mux_b = Wire(in.b)
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val ok_r = Wire(in.r)
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val err_r = Wire(in.r)
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val mux_r = Wire(in.r)
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val d_resp = Mux(out.d.bits.error, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
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val d_hasData = edgeOut.hasData(out.d.bits)
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@ -108,58 +117,33 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
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ok_r.valid := out.d.valid && d_hasData
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ok_b.valid := out.d.valid && !d_hasData
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ok_r.bits.id := out.d.bits.source >> 1
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ok_r.bits.id := out.d.bits.source >> addedBits
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ok_r.bits.data := out.d.bits.data
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ok_r.bits.resp := d_resp
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ok_r.bits.last := d_last
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r_err_out.ready := err_r.ready
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err_r.valid := r_err_out.valid
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err_r.bits.id := r_err_out.bits.id
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err_r.bits.data := out.d.bits.data // don't care
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err_r.bits.resp := AXI4Parameters.RESP_DECERR
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err_r.bits.last := r_err_out.bits.last
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// AXI4 must hold R to one source until last
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val mux_lock_ok = RegInit(Bool(false))
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val mux_lock_err = RegInit(Bool(false))
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when (ok_r .fire()) { mux_lock_ok := !ok_r .bits.last }
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when (err_r.fire()) { mux_lock_err := !err_r.bits.last }
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assert (!mux_lock_ok || !mux_lock_err)
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// Prioritize err over ok (b/c err_r.valid comes from a register)
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mux_r.valid := (!mux_lock_err && ok_r.valid) || (!mux_lock_ok && err_r.valid)
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mux_r.bits := Mux(!mux_lock_ok && err_r.valid, err_r.bits, ok_r.bits)
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ok_r.ready := mux_r.ready && (mux_lock_ok || !err_r.valid)
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err_r.ready := mux_r.ready && !mux_lock_ok
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// AXI4 needs irrevocable behaviour
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in.r <> Queue.irrevocable(mux_r, 1, flow=true)
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in.r <> Queue.irrevocable(ok_r, 1, flow=true)
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ok_b.bits.id := out.d.bits.source >> 1
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ok_b.bits.id := out.d.bits.source >> addedBits
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ok_b.bits.resp := d_resp
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w_err_out.ready := err_b.ready
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err_b.valid := w_err_out.valid
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err_b.bits.id := w_err_out.bits
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err_b.bits.resp := AXI4Parameters.RESP_DECERR
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// Prioritize err over ok (b/c err_b.valid comes from a register)
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mux_b.valid := ok_b.valid || err_b.valid
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mux_b.bits := Mux(err_b.valid, err_b.bits, ok_b.bits)
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ok_b.ready := mux_b.ready && !err_b.valid
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err_b.ready := mux_b.ready
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// AXI4 needs irrevocable behaviour
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in.b <> Queue.irrevocable(mux_b, 1, flow=true)
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val q_b = Queue.irrevocable(ok_b, 1, flow=true)
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// Update flight trackers
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val r_set = in.ar.fire().asUInt << in.ar.bits.id
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val r_clr = (in.r.fire() && in.r.bits.last).asUInt << in.r.bits.id
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r_inflight := (r_inflight | r_set) & ~r_clr
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val w_set = in.aw.fire().asUInt << in.aw.bits.id
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val w_clr = in.b.fire().asUInt << in.b.bits.id
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w_inflight := (w_inflight | w_set) & ~w_clr
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// We need to prevent sending B valid before the last W beat is accepted
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// TileLink allows early acknowledgement of a write burst, but AXI does not.
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val b_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) })
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val b_allow = b_count(in.b.bits.id) =/= w_count(in.b.bits.id)
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val b_sel = UIntToOH(in.b.bits.id, numIds)
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(b_sel.toBools zip b_count) foreach { case (s, r) =>
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when (in.b.fire() && s) { r := r + UInt(1) }
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}
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in.b.bits := q_b.bits
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in.b.valid := q_b.valid && b_allow
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q_b.ready := in.b.ready && b_allow
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// Unused channels
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out.b.ready := Bool(true)
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