riscv/rocket-chip
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rocketchip: fix uses of AXI4 Fragmenter

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This commit is contained in:
Wesley W. Terpstra 2017-04-20 18:54:50 -07:00
parent e100a943ea
commit ca2cb033cd
4 changed files with 13 additions and 9 deletions
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2
src/main/scala/rocketchip/Configs.scala
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@ -42,7 +42,7 @@ class BasePlatformConfig extends Config((site, here, up) => {
case ErrorConfig => ErrorConfig(Seq(AddressSet(0x1000, 0xfff)))
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=4)
})
/** Actual elaboratable target Configs */

6
src/main/scala/rocketchip/Periphery.scala
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@ -238,12 +238,14 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << config.idBits))))))
private val fifoBits = 1
fsb.node :=
TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)(
AXI4ToTL()(
AXI4UserYanker(1 << (config.sourceBits - fifoBits - 1))(
AXI4Fragmenter()(
l2FrontendAXI4Node))))
AXI4IdIndexer(fifoBits)(
l2FrontendAXI4Node)))))
}
trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle {

2
src/main/scala/rocketchip/TestHarness.scala
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@ -53,7 +53,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
for (i <- 0 until channels) {
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))
sram.node := AXI4Buffer()(AXI4Fragmenter()(node))
}
lazy val module = new LazyModuleImp(this) {

12
src/main/scala/uncore/axi4/Test.scala
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@ -26,8 +26,8 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
ram.node := AXI4Fragmenter()(TLToAXI4(0, true )(xbar.node))
gpio.node := AXI4Fragmenter()(TLToAXI4(0, false)(xbar.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished
@ -49,8 +49,8 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
ram.node := AXI4Fragmenter()(TLToAXI4(4,false)(xbar.node))
gpio.node := AXI4Fragmenter()(TLToAXI4(4,true )(xbar.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished
@ -97,8 +97,10 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
AXI4ToTL()(
AXI4UserYanker(4)(
AXI4Fragmenter()(
node))))))
AXI4IdIndexer(4)(
node))))))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {