dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701)
* dcache: put a flow Q to absorb back-pressure without restarting pipeline When used with a RationalCrossing, pipelined MMIO does not come out cleanly. The first beat works, but if the second beat gets stalled, the pipeline is restarted. This is a quick hacky test to absorb the beats. Perhaps a better fix can be made to achieve the same effect. * dcache: provision as few stages as possible
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@ -11,6 +11,7 @@ import uncore.tilelink2._
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import uncore.util._
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import util._
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import TLMessages._
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import scala.math.min
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class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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val addr = Bits(width = untagBits)
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@ -57,6 +58,19 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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data.io.req <> dataArb.io.out
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dataArb.io.out.ready := true
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val rational = p(coreplex.RocketCrossing) match {
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case coreplex.SynchronousCrossing(_) => true
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case _ => false
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}
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val tl_out_a = Wire(tl_out.a)
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val q_depth = if (rational) min(2, maxUncachedInFlight-1) else 0
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if (q_depth <= 0) {
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tl_out.a <> tl_out_a
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} else {
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tl_out.a <> Queue(tl_out_a, q_depth, flow = true, pipe = true)
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}
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val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
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val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))
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val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire()) // TODO has data now :(
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@ -176,7 +190,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param)
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val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH)
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val s2_update_meta = s2_hit_state =/= s2_new_hit_state
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io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR)
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io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out_a.ready && !uncachedInFlight.asUInt.andR)
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when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
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val s3_valid = Reg(next = s2_valid, init=Bool(false))
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@ -285,17 +299,17 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2))
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} else {
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// If no managers support atomics, assert fail if processor asks for them
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assert (!(tl_out.a.valid && pstore1_amo && s2_write && s2_uncached))
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assert (!(tl_out_a.valid && pstore1_amo && s2_write && s2_uncached))
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Wire(new TLBundleA(edge.bundle))
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}
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tl_out.a.valid := (s2_valid_cached_miss && !s2_victim_dirty) ||
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tl_out_a.valid := (s2_valid_cached_miss && !s2_victim_dirty) ||
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(s2_valid_uncached && !uncachedInFlight.asUInt.andR)
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tl_out.a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!pstore1_amo, put, atomics)))
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tl_out_a.bits := Mux(!s2_uncached, acquire, Mux(!s2_write, get, Mux(!pstore1_amo, put, atomics)))
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// Set pending bits for outstanding TileLink transaction
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val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset
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when (tl_out.a.fire()) {
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when (tl_out_a.fire()) {
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when (s2_uncached) {
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(a_sel.toBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) =>
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when (s) {
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@ -518,7 +532,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val flushed = Reg(init=Bool(true))
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val flushing = Reg(init=Bool(false))
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val flushCounter = Counter(nSets * nWays)
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when (tl_out.a.fire() && !s2_uncached) { flushed := false }
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when (tl_out_a.fire() && !s2_uncached) { flushed := false }
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when (s2_valid_masked && s2_req.cmd === M_FLUSH_ALL) {
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io.cpu.s2_nack := !flushed
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when (!flushed) {
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@ -542,6 +556,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// performance events
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io.cpu.acquire := edge.done(tl_out.a)
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io.cpu.acquire := edge.done(tl_out_a)
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io.cpu.release := edge.done(tl_out.c)
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}
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