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axi4: SRAM support 0 userBits

This commit is contained in:
Wesley W. Terpstra 2017-05-08 00:30:40 -07:00
parent db76ff2d86
commit 3209e58845
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/uncore/axi4/SRAM.scala
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@ -40,7 +40,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
val w_full = RegInit(Bool(false))
val w_id = Reg(UInt())
val w_user = Reg(UInt())
val w_user = Reg(UInt(width = 1 max in.params.userBits))
when (in. b.fire()) { w_full := Bool(false) }
when (in.aw.fire()) { w_full := Bool(true) }
@ -65,7 +65,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
val r_full = RegInit(Bool(false))
val r_id = Reg(UInt())
val r_user = Reg(UInt())
val r_user = Reg(UInt(width = 1 max in.params.userBits))
when (in. r.fire()) { r_full := Bool(false) }
when (in.ar.fire()) { r_full := Bool(true) }