Basic L1 D$ ECC support
Only supports ECC on data, not tags; only supports byte granularity.
This commit is contained in:
Andrew Waterman
parent
6100600179
commit
6f8fdff762
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@ -15,7 +15,7 @@ import TLMessages._
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class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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val addr = Bits(width = untagBits)
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val write = Bool()
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val wdata = Bits(width = rowBits)
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val wdata = UInt(width = cacheParams.dataECC.width(cacheParams.dataECCBytes*8) * rowBytes/cacheParams.dataECCBytes)
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val wordMask = UInt(width = rowBytes / wordBytes)
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val byteMask = UInt(width = wordBytes)
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val way_en = Bits(width = nWays)
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@ -24,25 +24,26 @@ class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val io = new Bundle {
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val req = Valid(new DCacheDataReq).flip
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val resp = Vec(nWays, Bits(OUTPUT, rowBits))
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val resp = Vec(nWays, UInt(width = req.bits.wdata.getWidth)).asOutput
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}
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require(rowBytes % wordBytes == 0)
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val eccBytes = 1
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val eccBits = eccBytes * 8
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val eccMask = if (eccBytes == wordBytes) Seq(true.B) else (0 until wordBytes by eccBytes).map(io.req.bits.byteMask(_))
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val eccBits = cacheParams.dataECCBytes * 8
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val encBits = cacheParams.dataECC.width(eccBits)
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val encWordBits = encBits * (wordBits / eccBits)
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val eccMask = if (eccBits == wordBits) Seq(true.B) else (0 until wordBytes by eccBits/8).map(io.req.bits.byteMask(_))
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val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i)))
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val wWords = io.req.bits.wdata.grouped(encBits * (wordBits / eccBits))
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val addr = io.req.bits.addr >> rowOffBits
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val data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBytes / eccBytes), UInt(width = eccBits))) }
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val data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) }
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val rdata = for ((array, i) <- data_arrays zipWithIndex) yield {
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val valid = io.req.valid && (Bool(data_arrays.size == 1) || io.req.bits.wordMask(i))
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when (valid && io.req.bits.write) {
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val word = io.req.bits.wdata((i+1)*wordBits-1, i*wordBits)
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val wData = (0 until wordBits/eccBits).map(i => word((i+1)*eccBits-1, i*eccBits))
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val wData = wWords(i).grouped(encBits)
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array.write(addr, Vec((0 until nWays).flatMap(i => wData)), wMask)
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}
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val data = array.read(addr, valid && !io.req.bits.write)
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data.grouped(wordBytes / eccBytes).map(_.asUInt).toSeq
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data.grouped(wordBits / eccBits).map(_.asUInt).toSeq
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}
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(io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt }
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}
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@ -52,9 +53,13 @@ class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None)(im
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}
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class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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// no ECC support
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require(cacheParams.tagECC.isInstanceOf[IdentityCode])
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require(cacheParams.dataECC.isInstanceOf[IdentityCode])
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// no tag ECC support
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val tECC = cacheParams.tagECC
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val dECC = cacheParams.dataECC
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val eccBytes = cacheParams.dataECCBytes
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val eccBits = eccBytes * 8
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require(tECC.isInstanceOf[IdentityCode])
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require(eccBytes == 1)
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// tags
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val replacer = cacheParams.replacement
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@ -66,6 +71,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val data = Module(new DCacheDataArray)
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val dataArb = Module(new Arbiter(new DCacheDataReq, 4))
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data.io.req <> dataArb.io.out
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data.io.req.bits.wdata := encodeData(dataArb.io.out.bits.wdata(rowBits-1, 0))
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dataArb.io.out.ready := true
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val rational = p(coreplex.RocketCrossing) match {
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@ -97,8 +103,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val cached_grant_wait = Reg(init=Bool(false))
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val release_ack_wait = Reg(init=Bool(false))
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val release_state = Reg(init=s_ready)
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val pstore1_valid = Wire(Bool())
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val pstore2_valid = Reg(Bool())
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val any_pstore_valid = Wire(Bool())
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val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty)
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val releaseWay = Wire(UInt())
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io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack
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@ -186,13 +191,20 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked)
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val s2_hit_valid = s2_hit_state.isValid()
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val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
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val s2_valid_hit = s2_valid_masked && s2_readwrite && s2_hit
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val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_hit && !(pstore1_valid || pstore2_valid) && !release_ack_wait
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val s2_data_decoded = decodeData(s2_data)
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val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
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val s2_data_error = s2_read && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx)
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val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
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val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
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val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && s2_hit
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val s2_valid_data_error = s2_valid_hit_pre_data_ecc && s2_data_error
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val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error
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val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_hit && !any_pstore_valid && !release_ack_wait
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val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR
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val s2_victimize = s2_valid_cached_miss || s2_flush_valid
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val s2_victimize = Bool(!usingDataScratchpad) && (s2_valid_cached_miss || s2_valid_data_error || s2_flush_valid)
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val s2_valid_uncached = s2_valid_miss && s2_uncached
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val s2_victim_way = Mux(s2_hit_valid && !s2_flush_valid, s2_hit_way, UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)))
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val s2_victim_tag = RegEnable(s1_victim_meta.tag, s1_valid_not_nacked || s1_flush_valid)
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val s2_victim_tag = Mux(s2_valid_data_error, s2_req.addr >> untagBits, RegEnable(s1_victim_meta.tag, s1_valid_not_nacked || s1_flush_valid))
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val s2_victim_state = Mux(s2_hit_valid && !s2_flush_valid, s2_hit_state, RegEnable(s1_victim_meta.coh, s1_valid_not_nacked || s1_flush_valid))
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val s2_victim_valid = s2_victim_state.isValid()
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val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param)
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@ -201,12 +213,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out_a.ready && !uncachedInFlight.asUInt.andR)
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when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
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val s3_valid = Reg(next = s2_valid, init=Bool(false))
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val s3_uncached = Reg(next = s2_uncached, init=Bool(false))
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when (s2_valid_cached_miss) {
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assert( !(s3_valid && s3_uncached) )
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}
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// load reservations
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val s2_lr = Bool(usingAtomics && !usingDataScratchpad) && s2_req.cmd === M_XLR
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val s2_sc = Bool(usingAtomics && !usingDataScratchpad) && s2_req.cmd === M_XSC
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@ -232,14 +238,18 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// pending store buffer
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val s2_correct = s2_data_error && !any_pstore_valid && Bool(usingDataScratchpad)
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val s2_valid_correct = s2_valid_hit_pre_data_ecc && s2_correct
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val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write)
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val pstore1_typ = RegEnable(s1_req.typ, s1_valid_not_nacked && s1_write)
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val pstore1_addr = RegEnable(s1_paddr, s1_valid_not_nacked && s1_write)
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val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write)
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val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write)
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val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write)
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val pstore1_storegen_data = Wire(init = pstore1_data)
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val pstore1_amo = Bool(usingAtomics) && isRead(pstore1_cmd)
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val pstore1_valid = Wire(Bool())
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val pstore2_valid = Reg(Bool())
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any_pstore_valid := pstore1_valid || pstore2_valid
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val pstore_drain_structural = pstore1_valid && pstore2_valid && ((s1_valid && s1_write) || pstore1_amo)
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val pstore_drain_opportunistic = !(io.cpu.req.valid && isRead(io.cpu.req.bits.cmd))
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val pstore_drain_on_miss = releaseInFlight || io.cpu.s2_nack
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@ -253,17 +263,17 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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pstore1_held := (s2_store_valid || pstore1_held) && pstore2_valid && !pstore_drain
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s2_store_valid || pstore1_held
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}
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val advance_pstore1 = pstore1_valid && (pstore2_valid === pstore_drain)
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val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain)
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pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1
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val pstore2_addr = RegEnable(pstore1_addr, advance_pstore1)
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val pstore2_way = RegEnable(pstore1_way, advance_pstore1)
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val pstore2_addr = RegEnable(Mux(s2_correct, s2_req.addr, pstore1_addr), advance_pstore1)
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val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1)
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val pstore2_storegen_data = RegEnable(pstore1_storegen_data, advance_pstore1)
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val pstore2_storegen_mask = RegEnable(pstore1_mask, advance_pstore1)
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val pstore2_storegen_mask = RegEnable(~Mux(s2_correct, 0.U, ~pstore1_mask), advance_pstore1)
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dataArb.io.in(0).valid := pstore_drain
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dataArb.io.in(0).bits.write := true
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dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr)
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dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way)
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dataArb.io.in(0).bits.wdata := Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_storegen_data))
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dataArb.io.in(0).bits.wdata := Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data))
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dataArb.io.in(0).bits.wordMask := UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1,offsetlsb))
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dataArb.io.in(0).bits.byteMask := Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)
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@ -360,7 +370,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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}
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when (grantIsUncachedData) {
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s2_data := tl_out.d.bits.data
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s2_data := dummyEncodeData(tl_out.d.bits.data)
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s2_req.cmd := M_XRD
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s2_req.typ := req.typ
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s2_req.tag := req.tag
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@ -433,7 +443,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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toAddress = probe_bits.address,
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lgSize = lgCacheBlockBytes,
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shrinkPermissions = s2_shrink_param,
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data = s2_data)._2
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data = 0.U)._2
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} else {
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Wire(new TLBundleC(edge.bundle))
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}
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@ -445,7 +455,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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edge.ProbeAck(
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b = probe_bits,
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reportPermissions = s2_report_param,
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data = s2_data))
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data = 0.U))
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tl_out.c.valid := s2_release_data_valid
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tl_out.c.bits := nackResponseMessage
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@ -453,7 +463,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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releaseWay := s2_probe_way
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when (s2_victimize && s2_victim_dirty) {
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assert(!(s2_valid && s2_hit_valid))
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assert(!(s2_valid && s2_hit_valid && !s2_data_error))
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release_state := s_voluntary_writeback
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probe_bits.address := Cat(s2_victim_tag, s2_req.addr(idxMSB, idxLSB)) << idxLSB
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}
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@ -482,7 +492,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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when (s2_probe && !tl_out.c.fire()) { s1_nack := true }
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tl_out.c.bits.address := probe_bits.address
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tl_out.c.bits.data := s2_data
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tl_out.c.bits.data := s2_data_corrected
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dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles
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dataArb.io.in(2).bits.write := false
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@ -519,8 +529,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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// load data subword mux/sign extension
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val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
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val s2_data_word = s2_data >> Cat(s2_word_idx, UInt(0, log2Up(coreDataBits)))
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val s2_data_word = ((0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)): Seq[UInt])(s2_word_idx)
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val s2_data_word_corrected = ((0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)): Seq[UInt])(s2_word_idx)
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val loadgen = new LoadGen(s2_req.typ, mtSigned(s2_req.typ), s2_req.addr, s2_data_word, s2_sc, wordBytes)
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io.cpu.resp.bits.data := loadgen.data | s2_sc_fail
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io.cpu.resp.bits.data_word_bypass := loadgen.wordData
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@ -538,6 +548,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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} else {
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assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation")
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}
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when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected }
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// flushes
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val flushed = Reg(init=Bool(true))
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@ -570,4 +581,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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io.cpu.perf.acquire := edge.done(tl_out_a)
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io.cpu.perf.release := edge.done(tl_out.c)
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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def encodeData(x: UInt) = x.grouped(eccBits).map(dECC.encode(_)).asUInt
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def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt
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def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_))
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}
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@ -22,6 +22,7 @@ case class DCacheParams(
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nTLBEntries: Int = 32,
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tagECC: Code = new IdentityCode,
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dataECC: Code = new IdentityCode,
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dataECCBytes: Int = 1,
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nMSHRs: Int = 1,
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nSDQ: Int = 17,
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nRPQ: Int = 16,
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