riscv/rocket-chip
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axi4: massage test cases into shape again

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This commit is contained in:
Wesley W. Terpstra 2017-04-25 17:56:06 -07:00
parent 9f08c484bd
commit e1a072a644
3 changed files with 19 additions and 11 deletions
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16
src/main/scala/rocketchip/Periphery.scala
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@ -134,12 +134,16 @@ trait PeripheryMasterAXI4Mem {
beatBytes = config.beatBytes)
})
private val converter = LazyModule(new TLToAXI4(config.idBits))
private val converter = LazyModule(new TLToAXI4(config.beatBytes))
private val trim = LazyModule(new AXI4IdIndexer(config.idBits))
private val yank = LazyModule(new AXI4UserYanker)
private val buffer = LazyModule(new AXI4Buffer)
mem foreach { case xbar =>
converter.node := xbar.node
buffer.node := converter.node
trim.node := converter.node
yank.node := trim.node
buffer.node := yank.node
mem_axi4 := buffer.node
}
}
@ -207,10 +211,12 @@ trait PeripheryMasterAXI4MMIO {
mmio_axi4 :=
AXI4Buffer()(
AXI4UserYanker()(
AXI4Deinterleaver(cacheBlockBytes)(
TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
AXI4IdIndexer(config.idBits)(
TLToAXI4(config.beatBytes)(
TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus
socBus.node))))
socBus.node))))))
}
trait PeripheryMasterAXI4MMIOBundle {
@ -241,7 +247,7 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
fsb.node :=
TLWidthWidget(config.beatBytes)(
AXI4ToTL()(
AXI4UserYanker(1 << (config.sourceBits - fifoBits - 1))(
AXI4UserYanker(Some(1 << (config.sourceBits - fifoBits - 1)))(
AXI4Fragmenter()(
AXI4IdIndexer(fifoBits)(
l2FrontendAXI4Node)))))

6
src/main/scala/uncore/axi4/Test.scala
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@ -26,8 +26,8 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(0, true )(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(0, false)(xbar.node)))
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4, true )(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4, false)(xbar.node)))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished
@ -104,7 +104,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
AXI4ToTL()(
AXI4UserYanker(4)(
AXI4UserYanker(Some(4))(
AXI4Fragmenter()(
AXI4IdIndexer(2)(
node))))))))

8
src/main/scala/uncore/axi4/UserYanker.scala
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@ -8,8 +8,10 @@ import config._
import diplomacy._
import uncore.tilelink2.UIntToOH1
class AXI4UserYanker(maxFlightPerId: Int)(implicit p: Parameters) extends LazyModule
class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) extends LazyModule
{
// !!! make maxFlightPerId a cap and maxFlight a per AXI4 Master parameter
val maxFlightPerId = capMaxFlight.getOrElse(8)
require (maxFlightPerId >= 1)
val node = AXI4AdapterNode(
@ -80,8 +82,8 @@ class AXI4UserYanker(maxFlightPerId: Int)(implicit p: Parameters) extends LazyMo
object AXI4UserYanker
{
// applied to the AXI4 source node; y.node := AXI4UserYanker(idBits, maxFlight)(x.node)
def apply(maxFlight: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val yanker = LazyModule(new AXI4UserYanker(maxFlight))
def apply(capMaxFlight: Option[Int] = None)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val yanker = LazyModule(new AXI4UserYanker(capMaxFlight))
yanker.node := x
yanker.node
}