riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Fix FPU control bug for div/sqrt 

I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
This commit is contained in:
Andrew Waterman 2017-06-09 13:35:38 -07:00
parent e69badb205
commit 76af15a6ff
1 changed files with 3 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/tile/FPU.scala
View File

@ -754,15 +754,10 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
if (cfg.divSqrt) {
val divSqrt_killed = Reg(Bool())
makeDivSqrt(FType.S, wb_ctrl.singleOut)
fLen match {
case 32 =>
case 64 => makeDivSqrt(FType.D, !wb_ctrl.singleOut)
}
def makeDivSqrt(t: FType, en: Bool) = {
for (t <- floatTypes) {
val tag = !mem_ctrl.singleOut // TODO typeTag
val divSqrt = Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0))
divSqrt.io.inValid := en && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
divSqrt.io.inValid := mem_reg_valid && tag === typeTag(t) && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)