riscv/rocket-chip
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rocket-chip/src/main
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Wesley W. Terpstra 4847c32599 tilelink: ToAXI4 - must interlock till last beat 
AXI4 makes no guarantee that bursts are handled atomicly.
Thus, you could be part-way through a read burst and suddenly
a write cuts ahead and is visible later, violating FIFO.
2017-05-08 00:17:06 -07:00
..
scala
tilelink: ToAXI4 - must interlock till last beat
2017-05-08 00:17:06 -07:00