Refactor frontend exception passing
Bundle them, and leverage regularity, so that if we have to add more exceptions in the future, we don't need to change so much code.
This commit is contained in:
Andrew Waterman
parent
cc2f87c214
commit
3e04a99f61
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@ -18,13 +18,21 @@ class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
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val speculative = Bool()
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}
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class FrontendExceptions extends Bundle {
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val pf = new Bundle {
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val inst = Bool()
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}
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val ae = new Bundle {
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val inst = Bool()
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}
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val btb = Valid(new BTBResp)
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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val pf = Bool()
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val ae = Bool()
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val xcpt = new FrontendExceptions
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val replay = Bool()
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}
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@ -83,9 +91,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_tlb_resp = Reg(tlb.io.resp)
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val s2_pf = s2_tlb_resp.pf.inst && !s2_tlb_resp.miss
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val s2_ae = s2_tlb_resp.ae.inst && !s2_tlb_resp.miss
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val s2_xcpt = s2_pf || s2_ae
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val s2_xcpt = !s2_tlb_resp.miss && fq.io.enq.bits.xcpt.asUInt.orR
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val s2_speculative = Reg(init=Bool(false))
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val fetchBytes = coreInstBytes * fetchWidth
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@ -163,8 +169,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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fq.io.enq.bits.data := icache.io.resp.bits
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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fq.io.enq.bits.pf := s2_pf
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fq.io.enq.bits.ae := s2_ae
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fq.io.enq.bits.xcpt := s2_tlb_resp
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fq.io.enq.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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fq.io.enq.bits.btb.valid := s2_btb_resp_valid
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fq.io.enq.bits.btb.bits := s2_btb_resp_bits
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@ -9,10 +9,8 @@ import tile._
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import util._
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class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
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val pf0 = Bool() // page fault on first half of instruction
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val pf1 = Bool() // page fault on second half of instruction
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val ae0 = Bool() // access exception on first half of instruction
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val ae1 = Bool() // access exception on second half of instruction
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val xcpt0 = new FrontendExceptions // exceptions on first half of instruction
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val xcpt1 = new FrontendExceptions // exceptions on second half of instruction
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val replay = Bool()
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val btb_hit = Bool()
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val rvc = Bool()
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@ -80,8 +78,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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val valid = (UIntToOH(nValid) - 1)(fetchWidth-1, 0)
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val bufMask = UIntToOH(nBufValid) - 1
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val pf = valid & (Mux(buf.pf, bufMask, UInt(0)) | Mux(io.imem.bits.pf, ~bufMask, UInt(0)))
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val ae = valid & (Mux(buf.ae, bufMask, UInt(0)) | Mux(io.imem.bits.ae, ~bufMask, UInt(0)))
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val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt))
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val ic_replay = valid & (Mux(buf.replay, bufMask, UInt(0)) | Mux(io.imem.bits.replay, ~bufMask, UInt(0)))
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val ibufBTBHitMask = Mux(ibufBTBHit, UIntToOH(ibufBTBResp.bridx), UInt(0))
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assert(!io.imem.valid || !io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
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@ -100,11 +97,9 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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if (usingCompressed) {
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val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))
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io.inst(i).valid := valid(j) && (exp.io.rvc || valid(j+1) || pf(j+1) || ae(j+1) || replay)
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io.inst(i).bits.pf0 := pf(j)
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io.inst(i).bits.pf1 := !exp.io.rvc && pf(j+1)
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io.inst(i).bits.ae0 := ae(j)
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io.inst(i).bits.ae1 := !exp.io.rvc && ae(j+1)
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io.inst(i).valid := valid(j) && (exp.io.rvc || valid(j+1) || xcpt(j+1).asUInt.orR || replay)
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io.inst(i).bits.xcpt0 := xcpt(j)
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io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1).asUInt).asTypeOf(new FrontendExceptions)
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io.inst(i).bits.replay := replay
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io.inst(i).bits.btb_hit := btbHitMask(j) || (!exp.io.rvc && btbHitMask(j+1))
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io.inst(i).bits.rvc := exp.io.rvc
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@ -115,10 +110,8 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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} else {
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when (io.inst(i).ready) { nReady := i+1 }
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io.inst(i).valid := valid(i)
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io.inst(i).bits.pf0 := pf(i)
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io.inst(i).bits.pf1 := false
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io.inst(i).bits.ae0 := ae(i)
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io.inst(i).bits.ae1 := false
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io.inst(i).bits.xcpt0 := xcpt(i)
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io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions)
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io.inst(i).bits.replay := ic_replay(i)
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io.inst(i).bits.rvc := false
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io.inst(i).bits.btb_hit := btbHitMask(i)
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@ -231,14 +231,16 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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bpu.io.pc := ibuf.io.pc
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bpu.io.ea := mem_reg_wdata
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val id_xcpt_pf = ibuf.io.inst(0).bits.pf0 || ibuf.io.inst(0).bits.pf1
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val id_xcpt_ae = ibuf.io.inst(0).bits.ae0 || ibuf.io.inst(0).bits.ae1
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val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
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val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
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val (id_xcpt, id_cause) = checkExceptions(List(
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(csr.io.interrupt, csr.io.interrupt_cause),
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(bpu.io.debug_if, UInt(CSR.debugTriggerCause)),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(id_xcpt_pf, UInt(Causes.fetch_page_fault)),
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(id_xcpt_ae, UInt(Causes.fetch_access)),
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(id_xcpt0.pf.inst, UInt(Causes.fetch_page_fault)),
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(id_xcpt0.ae.inst, UInt(Causes.fetch_access)),
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(id_xcpt1.pf.inst, UInt(Causes.fetch_page_fault)),
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(id_xcpt1.ae.inst, UInt(Causes.fetch_access)),
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(id_illegal_insn, UInt(Causes.illegal_instruction))))
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val dcache_bypass_data =
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@ -305,15 +307,15 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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ex_ctrl.alu_dw := DW_XPR
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ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction
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ex_ctrl.sel_alu2 := A2_ZERO
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when (bpu.io.xcpt_if || id_xcpt_pf || id_xcpt_ae) { // badaddr := PC
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when (id_xcpt1.asUInt.orR) { // badaddr := PC+2
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ex_ctrl.sel_alu1 := A1_PC
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}
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val pf_second = !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1
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val ae_second = !ibuf.io.inst(0).bits.ae0 && ibuf.io.inst(0).bits.ae1
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when (!bpu.io.xcpt_if && (pf_second || (!id_xcpt_pf && ae_second))) { // badaddr := PC+2
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ex_ctrl.sel_alu2 := A2_SIZE
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ex_reg_rvc := true
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}
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when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC
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ex_ctrl.sel_alu1 := A1_PC
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ex_ctrl.sel_alu2 := A2_ZERO
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}
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}
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ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
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ex_reg_load_use := id_load_use
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