coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887)
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@ -35,6 +35,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
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case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
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case PLICParams => PLICParams()
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case ClintParams => ClintParams()
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case DTSTimebase => BigInt(1000000) // 1 MHz
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// TileLink connection global parameters
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case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
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case TLCombinationalCheck => false
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@ -281,10 +282,6 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
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case NExtTopInterrupts => nExtInts
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})
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class WithRTCPeriod(nCycles: Int) extends Config((site, here, up) => {
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case RTCPeriod => nCycles
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})
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class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
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case BankedL2Params => up(BankedL2Params, site).copy(nMemoryChannels = n)
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})
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@ -7,12 +7,15 @@ import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.config.Field
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case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.default,
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slaveBuffering: BufferParams = BufferParams.none,
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arithmetic: Boolean = true
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arithmetic: Boolean = true,
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends TLBusParams {
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}
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@ -3,21 +3,22 @@
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.diplomacy.LazyMultiIOModuleImp
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import freechips.rocketchip.diplomacy.{LazyMultiIOModuleImp, DTSTimebase}
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import freechips.rocketchip.devices.tilelink.HasPeripheryClint
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/** Real-time clock is based on RTCPeriod relative to system clock.
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*/
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case object RTCPeriod extends Field[Option[Int]]
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trait HasRTCModuleImp extends LazyMultiIOModuleImp {
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val outer: HasPeripheryClint
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private val internalPeriod: Option[Int] = outer.p(RTCPeriod)
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require(internalPeriod.isDefined, "RTCPeriod is not defined")
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private val pbusFreq = outer.p(PeripheryBusParams).frequency
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private val rtcFreq = outer.p(DTSTimebase)
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private val internalPeriod: BigInt = pbusFreq / rtcFreq
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// check whether pbusFreq >= rtcFreq
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require(internalPeriod > 0)
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// check wehther the integer division is within 5% of the real division
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require((pbusFreq - rtcFreq * internalPeriod) * 100 / pbusFreq <= 5)
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// Use the static period to toggle the RTC
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val (_, int_rtc_tick) = Counter(true.B, internalPeriod.get)
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val (_, int_rtc_tick) = Counter(true.B, internalPeriod.toInt)
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outer.clint.module.io.rtcTick := int_rtc_tick
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}
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@ -14,8 +14,6 @@ class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) =>
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// DTS descriptive parameters
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case DTSModel => "freechips,rocketchip-unknown"
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case DTSCompat => Nil
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case DTSTimebase => BigInt(1000000) // 1 MHz
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case RTCPeriod => Some(1000) // Implies coreplex clock is DTSTimebase * RTCPeriod = 1 GHz
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// External port parameters
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case IncludeJtagDTM => false
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case JtagDTMKey => new JtagDTMKeyDefault()
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