riscv/rocket-chip
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groundtest: fix test ram width

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This commit is contained in:
Henry Cook 2017-06-20 18:05:08 -07:00
parent 2f2fe0a973
commit bf431c0a53
1 changed files with 1 additions and 1 deletions
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src/main/scala/groundtest/Coreplex.scala
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@ -44,7 +44,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
tile_splitter.node :=* fixer.node
tiles.foreach { fixer.node :=* _.masterNode }
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBlockBytes))
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBeatBytes))
pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))