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axi4: IdIndexer now handles 0-width IDs

This commit is contained in:
Wesley W. Terpstra 2017-05-07 13:10:51 -07:00
parent c6135a02df
commit 8169ba6411
1 changed files with 16 additions and 6 deletions
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22
src/main/scala/uncore/axi4/IdIndexer.scala
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@ -56,12 +56,22 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
val bits = log2Ceil(edgeIn.master.endId) - idBits
if (bits > 0) {
out.ar.bits.user.get := Cat(in.ar.bits.user.toList ++ Seq(in.ar.bits.id >> idBits))
out.aw.bits.user.get := Cat(in.aw.bits.user.toList ++ Seq(in.aw.bits.id >> idBits))
in.r.bits.user.foreach { _ := out.r.bits.user.get >> bits }
in.b.bits.user.foreach { _ := out.b.bits.user.get >> bits }
in.r.bits.id := Cat(out.r.bits.user.get, out.r.bits.id)
in.b.bits.id := Cat(out.b.bits.user.get, out.b.bits.id)
// (in.aX.bits.id >> idBits).width = bits > 0
out.ar.bits.user.get := Cat(in.ar.bits.user.toList ++ Seq(in.ar.bits.id >> idBits))
out.aw.bits.user.get := Cat(in.aw.bits.user.toList ++ Seq(in.aw.bits.id >> idBits))
// user.isDefined => width > 0
in.r.bits.user.foreach { _ := out.r.bits.user.get >> bits }
in.b.bits.user.foreach { _ := out.b.bits.user.get >> bits }
// Special care is needed in case of 0 idBits, b/c .id has width 1 still
if (idBits == 0) {
out.ar.bits.id := UInt(0)
out.aw.bits.id := UInt(0)
in.r.bits.id := out.r.bits.user.get
in.b.bits.id := out.b.bits.user.get
} else {
in.r.bits.id := Cat(out.r.bits.user.get, out.r.bits.id)
in.b.bits.id := Cat(out.b.bits.user.get, out.b.bits.id)
}
}
}
}