Henry Cook
c9e7874818
Major tilelink revision for uncached message types
2014-11-11 17:36:48 -08:00
Christopher Celio
fea31d2167
Significant changes and fixes to BTB for superscalar fetch.
...
- BTBUpdate only occurs on mispredicts now.
- RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
Decode).
- Added optional 2nd CAM port to BTB for updates (for when updates to the
BTB may occur out-of-order).
- Fixed resp.mask bit logic.
2014-11-11 03:34:05 -08:00
Christopher Celio
3be3cd7731
Fixed error with icache/btb resp mask.
2014-11-03 01:13:22 -08:00
Christopher Celio
08d2c13330
Fixed btb/icache bugs regarding resp mask, fw==1
2014-10-20 18:45:23 -07:00
Christopher Celio
91efdc379b
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Also fixed bridx logic and zero-width wire logic.
Conflicts:
src/main/scala/btb.scala
2014-10-14 18:10:29 -07:00
Christopher Celio
99614e37aa
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Conflicts:
src/main/scala/btb.scala
src/main/scala/core.scala
2014-10-03 04:22:58 -07:00
Christopher Celio
9cc35dee9a
Returned history update to fetch.
...
- Global history only contains branches.
- Only update BHT and history on BTB hits.
- Gate off speculative update on stall or icmiss.
- Fixed bug where BHT updates were delayed a cycle.
2014-09-29 21:41:07 -07:00
Christopher Celio
8ccd07cfeb
Moved updating global history from fetch to decode.
...
- No longer update global history in fetch stage.
- Only update global history when instruction is a branch.
- Does allow for the possibility of back-to-back branches to see
slightly different histories on subsequent executions.
2014-09-28 05:16:36 -07:00
Christopher Celio
681b43f398
Bug fixes with global history register.
...
- Updated in fetch speculatively.
* Updates gated off by cpu.resp.fire().
* BTB direction factored into history update.
- All branches update the BHT.
- Each instruction carries history; index into BHT is recomputed by
passing in mem_reg_pc.
2014-09-26 10:39:57 -07:00
Christopher Celio
180d3d365d
Expanded front-end to support superscalar fetch.
2014-09-17 14:24:03 -07:00
Yunsup Lee
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
Henry Cook
b42a2ab40a
Final parameter refactor
2014-09-01 13:28:58 -07:00
Henry Cook
6a4193cf90
minor cache param cleanup
2014-08-19 11:38:46 -07:00
Henry Cook
2de268b3b1
Cache utility traits. Completely compiles, asm tests hang.
2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467
Full conversion to params. Compiles but does not elaborate.
2014-08-19 11:38:02 -07:00
Andrew Waterman
4ca152b012
Use BundleWithConf to avoid clone method boilerplate
2014-05-09 19:37:16 -07:00
Henry Cook
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
Henry Cook
1da8ef2ddf
Added serdes to decouple cache row size from tilelink data size
2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
Andrew Waterman
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab
Add return address stack
2014-04-01 15:01:27 -07:00
Andrew Waterman
e3b12e0b85
Make BTB more complexity-effective
...
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
2014-03-25 05:22:04 -07:00
Andrew Waterman
804b09c8c5
Frontend QoR tweaks
2014-03-25 05:20:24 -07:00
Henry Cook
2c2b3a7678
cleanups supporting uncore hierarchy
2014-01-31 12:07:26 -08:00
Christopher Celio
a2be21361e
Allow ICacheConfig to toggle fetch-width.
2014-01-22 16:19:57 -08:00
Andrew Waterman
65b8340cea
Mitigate D$ hit -> branch -> NPC critical path
2013-11-24 14:21:03 -08:00
Andrew Waterman
1edb1e2a0a
Ignore LSB of PC
2013-09-12 17:55:58 -07:00
Henry Cook
d06e24ac24
new enum syntax
2013-09-10 10:51:35 -07:00
Henry Cook
3a266cbbfa
final Reg changes
2013-08-15 15:28:15 -07:00
Henry Cook
1a9e43aa11
initial attempt at upgrade
2013-08-12 10:39:11 -07:00
Henry Cook
4eaab214d2
Fold uncore constants into TileLinkConfiguration, update coherence API
2013-08-02 16:29:51 -07:00
Henry Cook
9abdf4e154
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
2013-07-23 20:27:58 -07:00
Henry Cook
569d8fd796
Merge branch 'tilelink-data'
2013-05-23 14:14:40 -07:00
Yunsup Lee
11133d6d4c
clock gate s2 registers in the frontend
2013-05-21 18:59:21 -07:00
Henry Cook
69b508ff39
ported caches and htif to use new tilelink
2013-05-21 17:21:04 -07:00
Yunsup Lee
dcde377303
Fix DM I$ deadlock
...
BTB predictions were causing infinite miss loops
2013-05-20 15:22:58 -07:00
Andrew Waterman
6eb4c2542a
comment out I$ assert for now
2013-05-18 18:09:23 -07:00
Andrew Waterman
dfa7a03f73
use assert, not Assert
2013-05-18 00:45:13 -07:00
Andrew Waterman
d405ffa949
assume all I$ grants bear data
2013-05-01 21:01:20 -07:00
Henry Cook
95f0a688e9
Merge branch 'release-xacts'
...
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
2013-03-20 15:53:36 -07:00
Andrew Waterman
ea9d0b771e
remove aborts; simplify probes
2013-03-19 15:29:40 -07:00
Henry Cook
e0361840bd
writebacks on release network pass asm tests and bmarks
2013-02-28 18:11:40 -08:00
Andrew Waterman
35349d227f
update to new Mem style
2013-02-20 16:09:46 -08:00
Henry Cook
f5729c9f25
removed ack_required field from grant messages
2013-01-28 16:44:17 -08:00
Rimas Avizienis
63060bc0a8
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74
New TileLink bundle names
2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d
Refactored packet headers/payloads
2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114
standardize IO naming convention
2013-01-07 13:41:36 -08:00
Andrew Waterman
de2f28193a
get rid of more global constants
2012-11-25 04:24:25 -08:00
Andrew Waterman
b514c7b725
clean up I$ parity code
2012-11-24 22:00:43 -08:00
Andrew Waterman
ff8c736d94
move icache invalidate out of request bundle
2012-11-16 01:55:45 -08:00
Andrew Waterman
4d1ca8ba3a
remove more global consts; refactor DTLBs
...
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
c5b93798fb
factor out more global constants
2012-11-05 23:52:32 -08:00
Andrew Waterman
e9eca6a95d
refactor I$ config; remove Top class
2012-11-04 16:59:36 -08:00
Andrew Waterman
bd2d61de03
use 8T SRAM for I$; gate clock more aggressively
2012-11-04 16:39:25 -08:00
Henry Cook
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
Andrew Waterman
5821900329
don't refetch from I$ if on same 16B block
2012-10-16 02:24:38 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2
improvements to implicit RocketConfiguration parameter
2012-10-15 16:29:49 -07:00
Henry Cook
9025d0610c
first pass at configuration object passed as implicit parameter
2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Huy Vo
e909093f37
factoring out uncore into separate uncore repo
2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5
uncore and rocket changes for new xact types
2012-10-01 10:47:36 -07:00
Andrew Waterman
0f20771664
rename queue to Queue
...
fixes build with case-insensitive file system
2012-08-08 22:11:59 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3
use only one (wide) tag ram for set assoc. caches
2012-07-12 14:50:12 -07:00
Andrew Waterman
4e5f874266
update to new chisel/hwacha
2012-06-08 00:13:14 -07:00
Huy Vo
04304fe788
moving util out into Chisel standard library
2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44
views removed
2012-06-06 12:51:26 -07:00
Andrew Waterman
7f6319047e
update to new scala/chisel/Mem
2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
Andrew Waterman
eafdffe125
simplify page table walker; speed up emulator
2012-05-01 01:24:36 -07:00
Henry Cook
3cdd166153
Refactored coherence as member rather than trait. MI and MEI protocols.
2012-04-10 00:09:58 -07:00
Henry Cook
0b4937f70f
changed coherence message type names
2012-04-09 23:29:31 -07:00
Yunsup Lee
32d95e9594
fix -1:0 index problem for direct map case
2012-03-26 17:00:01 -07:00
Henry Cook
22726ae646
icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
2012-03-08 18:47:32 -08:00
Andrew Waterman
6e16b04ada
implement transaction finish messages
2012-03-06 15:48:08 -08:00
Andrew Waterman
5f12990dfb
support memory transaction aborts
2012-03-06 00:35:02 -08:00
Henry Cook
1b3307df32
Removed has_data fields from all coherence messages, increased message type names to compensate
2012-03-02 23:51:53 -08:00
Andrew Waterman
012da6002e
replace tile memory interface with ioTileLink
...
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
2012-02-29 03:10:47 -08:00
Andrew Waterman
c99f6bbeb7
separate memory request command and data
...
also, merge some VLSI/C++ test harness functionality
2012-02-28 19:06:23 -08:00
Andrew Waterman
2b1c07c723
replace ioDCache with ioMem
2012-02-27 18:36:09 -08:00
Andrew Waterman
ad713a5d83
fix icache ram depth; new chisel
2012-02-26 17:51:46 -08:00
Huy Vo
5b0f7ccf68
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
2012-02-26 17:24:08 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Andrew Waterman
6135615104
unify cache backend interfaces; generify arbiter
2012-02-20 00:51:48 -08:00
Andrew Waterman
725190d0ee
update to new chisel
2012-02-11 17:20:33 -08:00
Christopher Celio
1be9d15944
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
2012-02-07 14:07:42 -08:00
Henry Cook
c5a4eaa0a1
Associative cache, boots kernel
2012-02-01 13:26:04 -08:00
Andrew Waterman
97c379f1d7
made I$ associative
2012-01-24 16:51:30 -08:00
Andrew Waterman
7f26fe2c44
make icache size parameterizable
2012-01-24 15:13:49 -08:00
Andrew Waterman
a5a020f97b
update chisel and remove SRAM_READ_LATENCY
2012-01-23 20:59:38 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
addfe55735
add FPGA memory generator script
2012-01-13 18:19:08 -08:00
Andrew Waterman
4807d7222b
use replay to handle I$ misses
...
this eliminates a long path in the fetch stage
2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350
remove icache req_rdy signal
2012-01-11 18:27:11 -08:00
Andrew Waterman
a8d0cd95e6
hellacache now works
2011-12-17 03:26:11 -08:00