riscv/rocket-chip
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Fix DM I$ deadlock

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BTB predictions were causing infinite miss loops
This commit is contained in:
Yunsup Lee 2013-05-20 15:22:58 -07:00
parent 3a1b5f01b2
commit dcde377303
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/icache.scala
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@ -110,7 +110,7 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex
icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
icache.io.invalidate := io.cpu.invalidate
icache.io.req.bits.ppn := tlb.io.resp.ppn
icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss
icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss
icache.io.resp.ready := !stall && !s1_same_block
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)