first pass at configuration object passed as implicit parameter
This commit is contained in:
Henry Cook
parent
dfdfddebe8
commit
9025d0610c
@ -1,19 +1,19 @@
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package rocket
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import Chisel._;
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import Node._;
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import Constants._;
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import Chisel._
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import Node._
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import Constants._
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import hwacha._
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class ioRocket extends Bundle()
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class ioRocket()(implicit conf: Configuration) extends Bundle
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{
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val host = new ioHTIF
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val host = new ioHTIF()
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val imem = (new ioImem).flip
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val vimem = (new ioImem).flip
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val dmem = new ioHellaCache
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}
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class rocketProc extends Component
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class rocketProc()(implicit conf: Configuration) extends Component
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{
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val io = new ioRocket
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@ -12,9 +12,9 @@ class ioDpathImem extends Bundle()
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val resp_data = Bits(INPUT, 32);
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}
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class ioDpathAll extends Bundle()
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class ioDpathAll()(implicit conf: Configuration) extends Bundle()
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{
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val host = new ioHTIF();
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val host = new ioHTIF()
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val ctrl = new ioCtrlDpath().flip
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val dmem = new ioHellaCache
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val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
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@ -28,7 +28,7 @@ class ioDpathAll extends Bundle()
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val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN)
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}
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class rocketDpath extends Component
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class rocketDpath()(implicit conf: Configuration) extends Component
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{
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val io = new ioDpathAll();
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@ -57,7 +57,7 @@ class rocketDpathBTB(entries: Int) extends Component
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io.target := mux.io.out.toUFix
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}
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class ioDpathPCR extends Bundle()
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class ioDpathPCR()(implicit conf: Configuration) extends Bundle()
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{
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val host = new ioHTIF()
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val r = new ioReadPort();
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@ -86,7 +86,7 @@ class ioDpathPCR extends Bundle()
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val vec_nfregs = UFix(INPUT, 6)
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}
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class rocketDpathPCR extends Component
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class rocketDpathPCR()(implicit conf: Configuration) extends Component
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{
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val io = new ioDpathPCR();
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@ -23,21 +23,21 @@ class PCRReq extends Bundle
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val data = Bits(width = 64)
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}
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class ioHTIF extends Bundle
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class ioHTIF()(implicit conf: Configuration) extends Bundle
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{
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val reset = Bool(INPUT)
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val debug = new ioDebug
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val pcr_req = (new FIFOIO) { new PCRReq }.flip
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val pcr_rep = (new FIFOIO) { Bits(width = 64) }
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val ipi_req = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
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val ipi_req = (new FIFOIO) { Bits(width = log2Up(conf.ntiles)) }
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val ipi_rep = (new FIFOIO) { Bool() }.flip
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}
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class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component
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class rocketHTIF(w: Int)(implicit conf: Configuration) extends Component
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{
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val io = new Bundle {
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val host = new ioHost(w)
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val cpu = Vec(ncores) { new ioHTIF().flip }
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val cpu = Vec(conf.ntiles) { new ioHTIF().flip }
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val mem = new ioTileLink
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}
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@ -78,7 +78,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
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val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
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val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2Up(ncores),20)
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val pcr_coreid = if (conf.ntiles == 1) UFix(0) else addr(20+log2Up(conf.ntiles),20)
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val pcr_wdata = packet_ram(0)
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val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
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@ -178,7 +178,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
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}
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x_init.io.enq.valid := state === state_mem_req
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val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
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x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0)))
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x_init.io.enq.bits := Mux(cmd === cmd_writemem, conf.co.getUncachedWriteTransactionInit(init_addr, UFix(0)), conf.co.getUncachedReadTransactionInit(init_addr, UFix(0)))
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io.mem.xact_init <> x_init.io.deq
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io.mem.xact_init_data.valid:= state === state_mem_wdata
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io.mem.xact_init_data.bits.data := mem_req_data
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@ -189,8 +189,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
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io.mem.probe_rep_data.valid := Bool(false)
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io.mem.incoherent := Bool(true)
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val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }
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for (i <- 0 until ncores) {
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val pcr_mux = (new Mux1H(conf.ntiles)) { Bits(width = 64) }
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for (i <- 0 until conf.ntiles) {
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val my_reset = Reg(resetVal = Bool(true))
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val my_ipi = Reg(resetVal = Bool(false))
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val rdata = Reg() { Bits() }
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@ -208,7 +208,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
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}
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cpu.ipi_rep.valid := my_ipi
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cpu.ipi_req.ready := Bool(true)
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for (j <- 0 until ncores) {
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for (j <- 0 until conf.ntiles) {
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when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
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my_ipi := Bool(true)
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}
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@ -28,7 +28,7 @@ class ioRocketICache extends Bundle()
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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// parameters :
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// lines = # cache lines
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class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
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class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component
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{
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val io = new ioRocketICache();
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@ -137,7 +137,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
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io.cpu.resp_data := data_mux.io.out
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io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
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io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
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io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
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io.mem.xact_finish <> finish_q.io.deq
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// control state machine
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@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle {
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val data = new MetaData()
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}
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class MSHR(id: Int, co: CoherencePolicy) extends Component {
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class MSHR(id: Int)(implicit conf: Configuration) extends Component {
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val io = new Bundle {
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val req_pri_val = Bool(INPUT)
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val req_pri_rdy = Bool(OUTPUT)
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@ -197,7 +197,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
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val req_cmd = io.req_bits.cmd
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val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA)
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val idx_match = req.idx === io.req_bits.idx
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val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val rpq = (new Queue(NRPQ)) { new RPQEntry }
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
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@ -221,7 +221,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
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when (refill_done) { state := s_drain_rpq }
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when (reply) {
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refill_count := refill_count + UFix(1)
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line_state := co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
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line_state := conf.co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
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}
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when (abort) { state := s_refill_req }
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}
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@ -243,13 +243,13 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
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}
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when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
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xacx_type := co.getTransactionInitTypeOnSecondaryMiss(req_cmd, co.newStateOnFlush(), io.mem_req.bits)
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xacx_type := conf.co.getTransactionInitTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
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}
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when ((state === s_invalid) && io.req_pri_val) {
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flush := req_cmd === M_FLA
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line_state := co.newStateOnFlush()
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line_state := conf.co.newStateOnFlush()
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refill_count := UFix(0)
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xacx_type := co.getTransactionInitTypeOnPrimaryMiss(req_cmd, co.newStateOnFlush())
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xacx_type := conf.co.getTransactionInitTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
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req := io.req_bits
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when (io.req_bits.tag_miss) {
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@ -268,7 +268,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
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io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid || (state === s_meta_clear)
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io.meta_req.bits.rw := Bool(true)
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io.meta_req.bits.idx := req.idx
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io.meta_req.bits.data.state := Mux(state === s_meta_clear, co.newStateOnFlush(), line_state)
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io.meta_req.bits.data.state := Mux(state === s_meta_clear, conf.co.newStateOnFlush(), line_state)
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io.meta_req.bits.data.tag := req.tag
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io.meta_req.bits.way_en := req.way_oh
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@ -293,7 +293,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
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io.replay.bits.way_oh := req.way_oh
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}
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class MSHRFile(co: CoherencePolicy) extends Component {
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class MSHRFile()(implicit conf: Configuration) extends Component {
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val io = new Bundle {
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val req = (new FIFOIO) { new MSHRReq }.flip
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val secondary_miss = Bool(OUTPUT)
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@ -346,7 +346,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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var refill_probe_rdy = Bool(true)
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for (i <- 0 to NMSHR-1) {
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val mshr = new MSHR(i, co)
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val mshr = new MSHR(i)
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tag_mux.io.sel(i) := mshr.io.idx_match
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tag_mux.io.in(i) := mshr.io.tag
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@ -415,7 +415,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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}
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class WritebackUnit(co: CoherencePolicy) extends Component {
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class WritebackUnit()(implicit conf: Configuration) extends Component {
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val io = new Bundle {
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val req = (new FIFOIO) { new WritebackReq() }.flip
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val probe = (new FIFOIO) { new WritebackReq() }.flip
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@ -475,7 +475,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
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io.data_req.bits.data := Bits(0)
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io.mem_req.valid := valid && !cmd_sent
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io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback()
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io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback()
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io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
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io.mem_req.bits.tile_xact_id := req.tile_xact_id
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io.mem_req_data.valid := data_req_fired && !is_probe
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@ -484,7 +484,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
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io.probe_rep_data.bits.data := io.data_resp
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}
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class ProbeUnit(co: CoherencePolicy) extends Component {
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class ProbeUnit()(implicit conf: Configuration) extends Component {
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val io = new Bundle {
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val req = (new FIFOIO) { new ProbeRequest }.flip
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val rep = (new FIFOIO) { new ProbeReply }
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@ -510,7 +510,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
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state := s_writeback_resp
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}
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when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) {
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state := Mux(hit && co.needsWriteback(line_state), s_writeback_req, s_invalid)
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state := Mux(hit && conf.co.needsWriteback(line_state), s_writeback_req, s_invalid)
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}
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when ((state === s_mshr_req) && io.mshr_req.ready) {
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state := s_meta_req
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@ -531,13 +531,13 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
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io.req.ready := state === s_invalid
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io.rep.valid := state === s_probe_rep && io.meta_req.ready
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io.rep.bits := co.newProbeReply(req, Mux(hit, line_state, co.newStateOnFlush()))
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io.rep.bits := conf.co.newProbeReply(req, Mux(hit, line_state, conf.co.newStateOnFlush))
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io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit
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io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
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io.meta_req.bits.rw := state === s_probe_rep
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io.meta_req.bits.idx := req.addr
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io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state)
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io.meta_req.bits.data.state := conf.co.newStateOnProbeRequest(req, line_state)
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io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS)
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io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req
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io.addr := req.addr
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@ -548,7 +548,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
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io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
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}
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class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
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class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component {
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val io = new Bundle {
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val req = (new FIFOIO) { Bool() }.flip
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val meta_req = (new FIFOIO) { new MetaArrayReq() }
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@ -593,7 +593,7 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
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io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS)
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io.meta_req.bits.idx := idx_cnt
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io.meta_req.bits.rw := (state === s_reset)
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io.meta_req.bits.data.state := co.newStateOnFlush()
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io.meta_req.bits.data.state := conf.co.newStateOnFlush()
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io.meta_req.bits.data.tag := UFix(0)
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}
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@ -748,7 +748,7 @@ class ioHellaCache extends Bundle {
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val xcpt = (new HellaCacheExceptions).asInput
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}
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class HellaCache(co: CoherencePolicy) extends Component {
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class HellaCache()(implicit conf: Configuration) extends Component {
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val io = new Bundle {
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val cpu = (new ioHellaCache).flip
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val mem = new ioTileLink
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@ -801,10 +801,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
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val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
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val nack_hit = Bool()
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val wb = new WritebackUnit(co)
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val prober = new ProbeUnit(co)
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val mshr = new MSHRFile(co)
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val flusher = new FlushUnit(lines, co)
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val wb = new WritebackUnit
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val prober = new ProbeUnit
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val mshr = new MSHRFile
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val flusher = new FlushUnit(lines)
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val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool
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// reset and flush unit
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@ -863,10 +863,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
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val early_tag_nack = !meta_arb.io.in(3).ready
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val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn)
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val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
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val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_match_arr = (0 until NWAYS).map( w => conf.co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
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val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
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val tag_hit_arr = (0 until NWAYS).map( w => co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_hit_arr = (0 until NWAYS).map( w => conf.co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR
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val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en)
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val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en)
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@ -892,7 +892,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
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data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
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data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
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data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
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data_arb.io.in(0).valid := io.mem.xact_rep.valid && co.messageUpdatesDataArray(io.mem.xact_rep.bits)
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data_arb.io.in(0).valid := io.mem.xact_rep.valid && conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits)
|
||||
|
||||
// load hits
|
||||
data_arb.io.in(4).bits.offset := io.cpu.req.bits.idx(offsetmsb,ramindexlsb)
|
||||
@ -922,7 +922,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
|
||||
p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
|
||||
|
||||
// tag update after a store to an exclusive clean line.
|
||||
val new_hit_state = co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
|
||||
val new_hit_state = conf.co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
|
||||
val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
|
||||
meta.io.state_req.bits.rw := Bool(true)
|
||||
meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
|
||||
@ -946,7 +946,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
|
||||
// miss handling
|
||||
mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
|
||||
mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
|
||||
mshr.io.req.bits.old_dirty := co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
|
||||
mshr.io.req.bits.old_dirty := conf.co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
|
||||
mshr.io.req.bits.old_tag := meta_wb_mux.tag
|
||||
mshr.io.req.bits.tag := cpu_req_tag
|
||||
mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
|
||||
|
||||
@ -5,7 +5,7 @@ import Node._
|
||||
import Constants._
|
||||
import uncore._
|
||||
|
||||
class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal)
|
||||
class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal)
|
||||
{
|
||||
val io = new Bundle {
|
||||
val tilelink = new ioTileLink
|
||||
@ -13,8 +13,8 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
|
||||
}
|
||||
|
||||
val cpu = new rocketProc
|
||||
val icache = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
|
||||
val dcache = new HellaCache(co)
|
||||
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
|
||||
val dcache = new HellaCache
|
||||
|
||||
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
|
||||
arbiter.io.requestor(0) <> dcache.io.mem
|
||||
@ -31,7 +31,7 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
|
||||
|
||||
if (HAVE_VEC)
|
||||
{
|
||||
val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB)
|
||||
val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
|
||||
arbiter.io.requestor(2) <> vicache.io.mem
|
||||
cpu.io.vimem <> vicache.io.cpu
|
||||
}
|
||||
|
||||
@ -13,6 +13,7 @@ object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants
|
||||
}
|
||||
import DummyTopLevelConstants._
|
||||
|
||||
case class Configuration(ntiles: Int, co: CoherencePolicyWithUncached)
|
||||
|
||||
class Top extends Component
|
||||
{
|
||||
@ -23,6 +24,7 @@ class Top extends Component
|
||||
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
|
||||
else new MICoherence
|
||||
}
|
||||
implicit val conf = Configuration(NTILES, co)
|
||||
|
||||
val io = new Bundle {
|
||||
val debug = new ioDebug
|
||||
@ -30,7 +32,7 @@ class Top extends Component
|
||||
val mem = new ioMemPipe
|
||||
}
|
||||
|
||||
val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co)
|
||||
val htif = new rocketHTIF(HTIF_WIDTH)
|
||||
val hub = new CoherenceHubBroadcast(NTILES+1, co)
|
||||
hub.io.tiles(NTILES) <> htif.io.mem
|
||||
io.host <> htif.io.host
|
||||
@ -44,7 +46,7 @@ class Top extends Component
|
||||
for (i <- 0 until NTILES) {
|
||||
val hl = htif.io.cpu(i)
|
||||
val tl = hub.io.tiles(i)
|
||||
val tile = new Tile(co, resetSignal = hl.reset)
|
||||
val tile = new Tile(resetSignal = hl.reset)
|
||||
|
||||
tile.io.host.reset := Reg(Reg(hl.reset))
|
||||
tile.io.host.pcr_req <> Queue(hl.pcr_req)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user