writebacks on release network pass asm tests and bmarks
This commit is contained in:
Henry Cook
parent
f5729c9f25
commit
e0361840bd
@ -61,29 +61,29 @@ class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Com
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val requestor = Vec(n) { new UncachedRequestorIO }.flip
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}
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var xi_bits = new Acquire
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xi_bits := io.requestor(n-1).acquire.bits.payload
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xi_bits.client_xact_id := Cat(io.requestor(n-1).acquire.bits.payload.client_xact_id, UFix(n-1, log2Up(n)))
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var acq_bits = new Acquire
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acq_bits := io.requestor(n-1).acquire.bits.payload
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acq_bits.client_xact_id := Cat(io.requestor(n-1).acquire.bits.payload.client_xact_id, UFix(n-1, log2Up(n)))
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for (i <- n-2 to 0 by -1)
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{
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var my_xi_bits = new Acquire
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my_xi_bits := io.requestor(i).acquire.bits.payload
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my_xi_bits.client_xact_id := Cat(io.requestor(i).acquire.bits.payload.client_xact_id, UFix(i, log2Up(n)))
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var my_acq_bits = new Acquire
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my_acq_bits := io.requestor(i).acquire.bits.payload
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my_acq_bits.client_xact_id := Cat(io.requestor(i).acquire.bits.payload.client_xact_id, UFix(i, log2Up(n)))
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xi_bits = Mux(io.requestor(i).acquire.valid, my_xi_bits, xi_bits)
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acq_bits = Mux(io.requestor(i).acquire.valid, my_acq_bits, acq_bits)
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}
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io.mem.acquire.bits.payload := xi_bits
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io.mem.acquire.bits.payload := acq_bits
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io.mem.acquire.valid := io.requestor.map(_.acquire.valid).reduce(_||_)
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io.requestor(0).acquire.ready := io.mem.acquire.ready
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for (i <- 1 until n)
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io.requestor(i).acquire.ready := io.requestor(i-1).acquire.ready && !io.requestor(i-1).acquire.valid
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var xf_bits = io.requestor(n-1).grant_ack.bits
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var ga_bits = io.requestor(n-1).grant_ack.bits
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for (i <- n-2 to 0 by -1)
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xf_bits = Mux(io.requestor(i).grant_ack.valid, io.requestor(i).grant_ack.bits, xf_bits)
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ga_bits = Mux(io.requestor(i).grant_ack.valid, io.requestor(i).grant_ack.bits, ga_bits)
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io.mem.grant_ack.bits := xf_bits
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io.mem.grant_ack.bits := ga_bits
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io.mem.grant_ack.valid := io.requestor.map(_.grant_ack.valid).reduce(_||_)
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io.requestor(0).grant_ack.ready := io.mem.grant_ack.ready
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for (i <- 1 until n)
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@ -172,7 +172,8 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
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val s2_miss = s2_valid && !s2_any_tag_hit
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rdy := state === s_ready && !s2_miss
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val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES)
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Assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.")
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val (rf_cnt, refill_done) = Counter(io.mem.grant.valid && !c.co.isVoluntary(io.mem.grant.bits.payload), REFILL_CYCLES)
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val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
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val enc_tagbits = c.code.width(c.tagbits)
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@ -223,7 +224,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
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for (i <- 0 until c.assoc) {
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val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) }
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val s1_dout = Reg(){ Bits() }
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when (io.mem.grant.valid && repl_way === UFix(i)) {
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when (io.mem.grant.valid && c.co.messageHasData(io.mem.grant.bits.payload) && repl_way === UFix(i)) {
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val d = io.mem.grant.bits.payload.data
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data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
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}
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@ -123,11 +123,18 @@ class DataWriteReq(implicit conf: DCacheConfig) extends Bundle {
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override def clone = new DataWriteReq().asInstanceOf[this.type]
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}
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class InternalProbe(implicit conf: DCacheConfig) extends Probe {
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val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
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override def clone = new InternalProbe().asInstanceOf[this.type]
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}
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class WritebackReq(implicit conf: DCacheConfig) extends Bundle {
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val tag = Bits(width = conf.tagbits)
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val idx = Bits(width = conf.idxbits)
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val way_en = Bits(width = conf.ways)
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val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
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val r_type = UFix(width = RELEASE_TYPE_MAX_BITS)
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override def clone = new WritebackReq().asInstanceOf[this.type]
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}
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@ -162,8 +169,9 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val req_bits = new MSHRReq().asInput
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val req_sdq_id = UFix(INPUT, log2Up(conf.nsdq))
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val idx_match = Bool(OUTPUT)
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val tag = Bits(OUTPUT, conf.tagbits)
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val idx_match = Bool(OUTPUT)
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val probe_idx_match = Bool(OUTPUT)
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val tag = Bits(OUTPUT, conf.tagbits)
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val mem_req = (new FIFOIO) { new Acquire }
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val mem_resp = new DataWriteReq().asOutput
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@ -172,6 +180,9 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val replay = (new FIFOIO) { new Replay() }
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val mem_abort = (new PipeIO) { new Abort }.flip
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val mem_rep = (new PipeIO) { new Grant }.flip
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val mem_probe = (new PipeIO) { new Probe }.flip
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val mem_probe_ready = Bool(OUTPUT)
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val self_probe = (new FIFOIO) { new InternalProbe }
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val mem_finish = (new FIFOIO) { new GrantAck }
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val wb_req = (new FIFOIO) { new WritebackReq }
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val probe_writeback = (new FIFOIO) { Bool() }.flip
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@ -181,29 +192,45 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UFix() }
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val state = Reg(resetVal = s_invalid)
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val acq_type = Reg { UFix() }
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val acquire_type = Reg { UFix() }
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val release_type = Reg { UFix() }
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val line_state = Reg { UFix() }
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val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) }
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val req = Reg { new MSHRReq() }
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val sent_wb_req = Reg { Bool() }
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val req_cmd = io.req_bits.cmd
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val req_idx = req.addr(conf.untagbits-1,conf.offbits)
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val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits)
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val probe_idx_match = req_idx === io.mem_probe.bits.addr(conf.untagbits-1,conf.offbits)
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val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id)
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val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id)
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val refill_done = reply && refill_count.andR
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val wb_done = reply && (state === s_wb_resp)
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val probe_wb_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.old_meta.tag
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val probe_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.addr >> conf.untagbits
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val handle_probe = (state != s_invalid) && probe_idx_match
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val kill_probe = sent_wb_req && probe_wb_tag_match && conf.co.pendingVoluntaryReleaseIsSufficient(release_type, io.mem_probe.bits.p_type)
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val probe_q = (new Queue(1, pipe = true, flow = true)) { new Probe }
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probe_q.io.enq.valid := io.mem_probe.valid && handle_probe && sent_wb_req && !kill_probe
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io.mem_probe_ready := probe_q.io.enq.ready && handle_probe
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probe_q.io.enq.bits := io.mem_probe.bits
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io.self_probe.valid := probe_q.io.deq.valid && (state != s_wb_resp)
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probe_q.io.deq.ready := io.self_probe.ready && (state != s_wb_resp)
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io.self_probe.bits := probe_q.io.deq.bits
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io.self_probe.bits.client_xact_id := UFix(id)
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val rpq = (new Queue(conf.nrpq)) { new Replay }
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd)
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rpq.io.enq.bits := io.req_bits
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rpq.io.enq.bits.sdq_id := io.req_sdq_id
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rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid
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val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id)
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val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id)
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val refill_done = reply && refill_count.andR
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val wb_done = reply && (state === s_wb_resp)
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val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck }
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finish_q.io.enq.valid := wb_done || refill_done
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finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits)
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finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id
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io.wb_req.valid := Bool(false)
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@ -241,17 +268,22 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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when (io.probe_writeback.valid && idx_match) {
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io.wb_req.valid := Bool(false)
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when (io.probe_writeback.bits) { state := s_refill_req }
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}.elsewhen (io.wb_req.ready) { state := s_wb_resp }
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}.elsewhen (io.wb_req.ready) {
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sent_wb_req := Bool(true)
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state := s_wb_resp
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}
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}
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when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
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acq_type := conf.co.getAcquireTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
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acquire_type := conf.co.getAcquireTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
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}
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when ((state === s_invalid) && io.req_pri_val) {
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line_state := conf.co.newStateOnFlush()
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refill_count := UFix(0)
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acq_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
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acquire_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
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release_type := conf.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
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req := io.req_bits
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sent_wb_req := Bool(false)
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state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_refill_req)
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when (io.req_bits.tag_match) {
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@ -265,6 +297,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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}
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io.idx_match := (state != s_invalid) && idx_match
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io.probe_idx_match := (state != s_invalid) && probe_idx_match
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io.mem_resp := req
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io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits
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io.tag := req.addr >> conf.untagbits
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@ -281,12 +314,13 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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io.wb_req.bits.idx := req_idx
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io.wb_req.bits.way_en := req.way_en
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io.wb_req.bits.client_xact_id := Bits(id)
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io.wb_req.bits.r_type := conf.co.getReleaseTypeOnVoluntaryWriteback()
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io.probe_writeback.ready := (state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match
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io.probe_refill.ready := (state != s_refill_resp && state != s_drain_rpq) || !idx_match
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io.mem_req.valid := state === s_refill_req
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io.mem_req.bits.a_type := acq_type
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io.mem_req.bits.a_type := acquire_type
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io.mem_req.bits.addr := Cat(io.tag, req_idx).toUFix
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io.mem_req.bits.client_xact_id := Bits(id)
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io.mem_finish <> finish_q.io.deq
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@ -319,7 +353,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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val mem_rep = (new PipeIO) { new Grant }.flip
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val mem_finish = (new FIFOIO) { new GrantAck }
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val wb_req = (new FIFOIO) { new WritebackReq }
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val probe = (new FIFOIO) { Bool() }.flip
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val mem_probe = (new FIFOIO) { new Probe }.flip
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val self_probe = (new FIFOIO) { new InternalProbe }
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val fence_rdy = Bool(OUTPUT)
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}
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@ -340,6 +375,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire }
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val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck }
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val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq }
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val self_probe_arb = (new Arbiter(conf.nmshr+1)) { new InternalProbe }
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val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() }
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val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() }
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@ -347,11 +383,18 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.addr >> conf.untagbits
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var idx_match = Bool(false)
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var probe_idx_match = Bool(false)
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var pri_rdy = Bool(false)
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var fence = Bool(false)
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var sec_rdy = Bool(false)
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var writeback_probe_rdy = Bool(true)
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var refill_probe_rdy = Bool(true)
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var mem_probe_rdy = Bool(false)
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self_probe_arb.io.in(0).valid := io.mem_probe.valid && !probe_idx_match
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self_probe_arb.io.in(0).bits := io.mem_probe.bits
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self_probe_arb.io.in(0).bits.client_xact_id := UFix(0) // DNC
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mem_probe_rdy = mem_probe_rdy || self_probe_arb.io.in(0).ready
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for (i <- 0 to conf.nmshr-1) {
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val mshr = new MSHR(i)
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@ -367,14 +410,16 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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mshr.io.req_bits := io.req.bits
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mshr.io.req_sdq_id := sdq_alloc_id
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mshr.io.mem_probe <> io.mem_probe
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mshr.io.meta_read <> meta_read_arb.io.in(i)
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mshr.io.meta_write <> meta_write_arb.io.in(i)
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mshr.io.mem_req <> mem_req_arb.io.in(i)
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mshr.io.mem_finish <> mem_finish_arb.io.in(i)
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mshr.io.wb_req <> wb_req_arb.io.in(i)
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mshr.io.self_probe <> self_probe_arb.io.in(i+1)
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mshr.io.replay <> replay_arb.io.in(i)
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mshr.io.probe_refill.valid := io.probe.valid && tag_match
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mshr.io.probe_writeback.valid := io.probe.valid
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mshr.io.probe_refill.valid := io.mem_probe.valid && tag_match
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mshr.io.probe_writeback.valid := io.mem_probe.valid
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mshr.io.probe_writeback.bits := wb_probe_match
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mshr.io.mem_abort <> io.mem_abort
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@ -385,8 +430,10 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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sec_rdy = sec_rdy || mshr.io.req_sec_rdy
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fence = fence || !mshr.io.req_pri_rdy
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idx_match = idx_match || mshr.io.idx_match
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probe_idx_match = probe_idx_match || mshr.io.probe_idx_match
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refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready
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writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready
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mem_probe_rdy = mem_probe_rdy || mshr.io.mem_probe_ready
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}
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alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
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@ -396,12 +443,14 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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mem_req_arb.io.out <> io.mem_req
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mem_finish_arb.io.out <> io.mem_finish
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wb_req_arb.io.out <> io.wb_req
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self_probe_arb.io.out <> io.self_probe
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.secondary_miss := idx_match
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io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id)
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io.fence_rdy := !fence
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io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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io.mem_probe.ready := mem_probe_rdy
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//io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd)
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io.replay.bits.data := sdq(RegEn(replay_arb.io.out.bits.sdq_id, free_sdq))
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@ -421,13 +470,11 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
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val meta_read = (new FIFOIO) { new MetaReadReq }
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val data_req = (new FIFOIO) { new DataReadReq() }
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val data_resp = Bits(INPUT, conf.bitsperrow)
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val mem_req = (new FIFOIO) { new Acquire }
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val mem_req_data = (new FIFOIO) { new AcquireData }
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val release = (new FIFOIO) { new Release }
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val release_data = (new FIFOIO) { new ReleaseData }
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}
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val valid = Reg(resetVal = Bool(false))
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val is_probe = Reg{Bool()}
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val r1_data_req_fired = Reg(resetVal = Bool(false))
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val r2_data_req_fired = Reg(resetVal = Bool(false))
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val cmd_sent = Reg{Bool()}
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@ -442,7 +489,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
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cnt := cnt + 1
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}
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||||
when (r2_data_req_fired && !Mux(is_probe, io.release_data.ready, io.mem_req_data.ready)) {
|
||||
when (r2_data_req_fired && !io.release_data.ready) {
|
||||
r1_data_req_fired := false
|
||||
r2_data_req_fired := false
|
||||
cnt := cnt - Mux[UFix](r1_data_req_fired, 2, 1)
|
||||
@ -452,20 +499,18 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
|
||||
valid := false
|
||||
}
|
||||
|
||||
when (valid && io.mem_req.ready) {
|
||||
when (valid && io.release.ready) {
|
||||
cmd_sent := true
|
||||
}
|
||||
}
|
||||
when (io.probe.fire()) {
|
||||
valid := true
|
||||
is_probe := true
|
||||
cmd_sent := true
|
||||
cnt := 0
|
||||
req := io.probe.bits
|
||||
}
|
||||
when (io.req.fire()) {
|
||||
valid := true
|
||||
is_probe := false
|
||||
cmd_sent := false
|
||||
cnt := 0
|
||||
req := io.req.bits
|
||||
@ -478,22 +523,21 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
|
||||
io.data_req.bits.way_en := req.way_en
|
||||
io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(REFILL_CYCLES)-1,0)) << conf.ramoffbits
|
||||
|
||||
io.mem_req.valid := valid && !cmd_sent
|
||||
io.mem_req.bits.a_type := conf.co.getAcquireTypeOnWriteback()
|
||||
io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
|
||||
io.mem_req.bits.client_xact_id := req.client_xact_id
|
||||
io.mem_req_data.valid := r2_data_req_fired && !is_probe
|
||||
io.mem_req_data.bits.data := io.data_resp
|
||||
io.release_data.valid := r2_data_req_fired && is_probe
|
||||
io.release.valid := valid && !cmd_sent
|
||||
io.release.bits.r_type := req.r_type
|
||||
io.release.bits.addr := Cat(req.tag, req.idx).toUFix
|
||||
io.release.bits.client_xact_id := req.client_xact_id
|
||||
io.release.bits.master_xact_id := UFix(0)
|
||||
io.release_data.valid := r2_data_req_fired
|
||||
io.release_data.bits.data := io.data_resp
|
||||
|
||||
io.meta_read.valid := fire
|
||||
io.meta_read.bits.addr := io.mem_req.bits.addr << conf.offbits
|
||||
io.meta_read.bits.addr := io.release.bits.addr << conf.offbits
|
||||
}
|
||||
|
||||
class ProbeUnit(implicit conf: DCacheConfig) extends Component {
|
||||
val io = new Bundle {
|
||||
val req = (new FIFOIO) { new Probe }.flip
|
||||
val req = (new FIFOIO) { new InternalProbe }.flip
|
||||
val rep = (new FIFOIO) { new Release }
|
||||
val meta_read = (new FIFOIO) { new MetaReadReq }
|
||||
val meta_write = (new FIFOIO) { new MetaWriteReq }
|
||||
@ -507,7 +551,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
|
||||
val state = Reg(resetVal = s_invalid)
|
||||
val line_state = Reg() { UFix() }
|
||||
val way_en = Reg() { Bits() }
|
||||
val req = Reg() { new Probe() }
|
||||
val req = Reg() { new InternalProbe }
|
||||
val hit = way_en.orR
|
||||
|
||||
when (state === s_meta_write && io.meta_write.ready) {
|
||||
@ -529,7 +573,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
|
||||
state := s_release
|
||||
line_state := io.line_state
|
||||
way_en := io.way_en
|
||||
when (!io.mshr_req.ready) { state := s_meta_read }
|
||||
//when (!io.mshr_req.ready) { state := s_meta_read }
|
||||
}
|
||||
when (state === s_meta_resp) {
|
||||
state := s_mshr_req
|
||||
@ -544,7 +588,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
|
||||
|
||||
io.req.ready := state === s_invalid && !reset
|
||||
io.rep.valid := state === s_release
|
||||
io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush))
|
||||
io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush), req.client_xact_id)
|
||||
|
||||
io.meta_read.valid := state === s_meta_read
|
||||
io.meta_read.bits.addr := req.addr << UFix(conf.offbits)
|
||||
@ -555,11 +599,13 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
|
||||
io.meta_write.bits.data.state := conf.co.newStateOnProbe(req, line_state)
|
||||
io.meta_write.bits.data.tag := req.addr >> UFix(conf.idxbits)
|
||||
|
||||
io.mshr_req.valid := state === s_mshr_req
|
||||
//io.mshr_req.valid := state === s_mshr_req
|
||||
io.wb_req.valid := state === s_writeback_req
|
||||
io.wb_req.bits.way_en := way_en
|
||||
io.wb_req.bits.idx := req.addr
|
||||
io.wb_req.bits.tag := req.addr >> UFix(conf.idxbits)
|
||||
io.wb_req.bits.r_type := UFix(0) // DNC
|
||||
io.wb_req.bits.client_xact_id := UFix(0) // DNC
|
||||
}
|
||||
|
||||
class MetaDataArray(implicit conf: DCacheConfig) extends Component {
|
||||
@ -919,8 +965,18 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
|
||||
mshr.io.mem_abort.valid := io.mem.abort.valid
|
||||
mshr.io.mem_abort.bits := io.mem.abort.bits.payload
|
||||
io.mem.abort.ready := Bool(true)
|
||||
mshr.io.mem_probe <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
|
||||
when (mshr.io.req.fire()) { replacer.miss }
|
||||
|
||||
io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready
|
||||
mshr.io.mem_req.ready := io.mem.acquire.ready && prober.io.req.ready
|
||||
io.mem.acquire.bits.payload := mshr.io.mem_req.bits
|
||||
//TODO io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_req) ???
|
||||
//TODO io.mem.acquire_data should be connected to uncached store data generator
|
||||
//io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(TODO)
|
||||
io.mem.acquire_data.valid := Bool(false)
|
||||
io.mem.acquire_data.bits.payload.data := UFix(0)
|
||||
|
||||
// replays
|
||||
readArb.io.in(1).valid := mshr.io.replay.valid
|
||||
readArb.io.in(1).bits := mshr.io.replay.bits
|
||||
@ -931,9 +987,12 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
|
||||
metaWriteArb.io.in(0) <> mshr.io.meta_write
|
||||
|
||||
// probes
|
||||
prober.io.req <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
|
||||
FIFOedLogicalNetworkIOWrapper(prober.io.rep) <> io.mem.release
|
||||
prober.io.mshr_req <> mshr.io.probe
|
||||
val releaseArb = (new Arbiter(2)) { new Release }
|
||||
FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
|
||||
|
||||
prober.io.req <> mshr.io.self_probe
|
||||
prober.io.rep <> releaseArb.io.in(1)
|
||||
//prober.io.mshr_req <> mshr.io.probe
|
||||
prober.io.wb_req <> wb.io.probe
|
||||
prober.io.way_en := s2_tag_match_way
|
||||
prober.io.line_state := s2_hit_state
|
||||
@ -953,6 +1012,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
|
||||
wb.io.meta_read <> metaReadArb.io.in(3)
|
||||
wb.io.data_req <> readArb.io.in(2)
|
||||
wb.io.data_resp := s2_data_corrected
|
||||
releaseArb.io.in(0) <> wb.io.release
|
||||
FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release_data
|
||||
|
||||
// store->load bypassing
|
||||
@ -1016,13 +1076,5 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
|
||||
io.cpu.resp.bits.data_subword := loadgen.byte
|
||||
io.cpu.resp.bits.store_data := s2_req.data
|
||||
|
||||
val acquire_arb = (new Arbiter(2)) { new Acquire }
|
||||
acquire_arb.io.in(0) <> wb.io.mem_req
|
||||
acquire_arb.io.in(1).valid := mshr.io.mem_req.valid && prober.io.req.ready
|
||||
mshr.io.mem_req.ready := acquire_arb.io.in(1).ready && prober.io.req.ready
|
||||
acquire_arb.io.in(1).bits := mshr.io.mem_req.bits
|
||||
io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(acquire_arb.io.out)
|
||||
|
||||
io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(wb.io.mem_req_data)
|
||||
io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_finish)
|
||||
}
|
||||
|
||||
@ -24,6 +24,7 @@ case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: Coherenc
|
||||
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
|
||||
{
|
||||
val memPorts = 2 + confIn.vec
|
||||
val dcachePortID = 0
|
||||
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
|
||||
implicit val lnConf = confIn.lnConf
|
||||
implicit val conf = confIn.copy(dcache = dcConf)
|
||||
@ -38,7 +39,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
|
||||
val dcache = new HellaCache
|
||||
|
||||
val arbiter = new MemArbiter(memPorts)
|
||||
arbiter.io.requestor(0) <> dcache.io.mem
|
||||
arbiter.io.requestor(dcachePortID) <> dcache.io.mem
|
||||
arbiter.io.requestor(1) <> icache.io.mem
|
||||
|
||||
io.tilelink.acquire <> arbiter.io.mem.acquire
|
||||
@ -47,8 +48,11 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
|
||||
arbiter.io.mem.grant <> io.tilelink.grant
|
||||
io.tilelink.grant_ack <> arbiter.io.mem.grant_ack
|
||||
dcache.io.mem.probe <> io.tilelink.probe
|
||||
io.tilelink.release <> dcache.io.mem.release
|
||||
io.tilelink.release_data <> dcache.io.mem.release_data
|
||||
io.tilelink.release.valid := dcache.io.mem.release.valid
|
||||
dcache.io.mem.release.ready := io.tilelink.release.ready
|
||||
io.tilelink.release.bits := dcache.io.mem.release.bits
|
||||
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortID, log2Up(memPorts))) // Mimic client id extension done by MemArbiter for Acquires from either cache)
|
||||
|
||||
if (conf.vec) {
|
||||
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user