riscv/rocket-chip
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improvements to implicit RocketConfiguration parameter

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This commit is contained in:
Henry Cook 2012-10-15 16:29:49 -07:00
parent a7a4e65690
commit 8970b635b2
8 changed files with 23 additions and 23 deletions
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8
rocket/src/main/scala/cpu.scala
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@ -5,7 +5,7 @@ import Node._
import Constants._
import hwacha._
class ioRocket()(implicit conf: Configuration) extends Bundle
class ioRocket(implicit conf: RocketConfiguration) extends Bundle
{
val host = new ioHTIF()
val imem = (new ioImem).flip
@ -13,12 +13,12 @@ class ioRocket()(implicit conf: Configuration) extends Bundle
val dmem = new ioHellaCache
}
class rocketProc()(implicit conf: Configuration) extends Component
class rocketProc(implicit conf: RocketConfiguration) extends Component
{
val io = new ioRocket
val ctrl = new rocketCtrl();
val dpath = new rocketDpath();
val ctrl = new rocketCtrl
val dpath = new rocketDpath
val dtlb = new rocketDTLB(DTLB_ENTRIES);
val itlb = new rocketITLB(ITLB_ENTRIES);

6
rocket/src/main/scala/dpath.scala
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@ -12,9 +12,9 @@ class ioDpathImem extends Bundle()
val resp_data = Bits(INPUT, 32);
}
class ioDpathAll()(implicit conf: Configuration) extends Bundle()
class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle
{
val host = new ioHTIF()
val host = new ioHTIF
val ctrl = new ioCtrlDpath().flip
val dmem = new ioHellaCache
val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
@ -28,7 +28,7 @@ class ioDpathAll()(implicit conf: Configuration) extends Bundle()
val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN)
}
class rocketDpath()(implicit conf: Configuration) extends Component
class rocketDpath(implicit conf: RocketConfiguration) extends Component
{
val io = new ioDpathAll();

8
rocket/src/main/scala/dpath_util.scala
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@ -57,9 +57,9 @@ class rocketDpathBTB(entries: Int) extends Component
io.target := mux.io.out.toUFix
}
class ioDpathPCR()(implicit conf: Configuration) extends Bundle()
class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
{
val host = new ioHTIF()
val host = new ioHTIF
val r = new ioReadPort();
val w = new ioWritePort();
@ -86,9 +86,9 @@ class ioDpathPCR()(implicit conf: Configuration) extends Bundle()
val vec_nfregs = UFix(INPUT, 6)
}
class rocketDpathPCR()(implicit conf: Configuration) extends Component
class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
{
val io = new ioDpathPCR();
val io = new ioDpathPCR
val reg_epc = Reg() { UFix() };
val reg_badvaddr = Reg() { UFix() };

4
rocket/src/main/scala/htif.scala
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@ -23,7 +23,7 @@ class PCRReq extends Bundle
val data = Bits(width = 64)
}
class ioHTIF()(implicit conf: Configuration) extends Bundle
class ioHTIF(implicit conf: RocketConfiguration) extends Bundle
{
val reset = Bool(INPUT)
val debug = new ioDebug
@ -33,7 +33,7 @@ class ioHTIF()(implicit conf: Configuration) extends Bundle
val ipi_rep = (new FIFOIO) { Bool() }.flip
}
class rocketHTIF(w: Int)(implicit conf: Configuration) extends Component
class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component
{
val io = new Bundle {
val host = new ioHost(w)

2
rocket/src/main/scala/icache.scala
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@ -28,7 +28,7 @@ class ioRocketICache extends Bundle()
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component
class rocketICache(sets: Int, assoc: Int)(implicit conf: RocketConfiguration) extends Component
{
val io = new ioRocketICache();

12
rocket/src/main/scala/nbdcache.scala
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@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle {
val data = new MetaData()
}
class MSHR(id: Int)(implicit conf: Configuration) extends Component {
class MSHR(id: Int)(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT)
@ -293,7 +293,7 @@ class MSHR(id: Int)(implicit conf: Configuration) extends Component {
io.replay.bits.way_oh := req.way_oh
}
class MSHRFile()(implicit conf: Configuration) extends Component {
class MSHRFile(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT)
@ -415,7 +415,7 @@ class MSHRFile()(implicit conf: Configuration) extends Component {
}
class WritebackUnit()(implicit conf: Configuration) extends Component {
class WritebackUnit(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new WritebackReq() }.flip
val probe = (new FIFOIO) { new WritebackReq() }.flip
@ -484,7 +484,7 @@ class WritebackUnit()(implicit conf: Configuration) extends Component {
io.probe_rep_data.bits.data := io.data_resp
}
class ProbeUnit()(implicit conf: Configuration) extends Component {
class ProbeUnit(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new ProbeRequest }.flip
val rep = (new FIFOIO) { new ProbeReply }
@ -548,7 +548,7 @@ class ProbeUnit()(implicit conf: Configuration) extends Component {
io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
}
class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component {
class FlushUnit(lines: Int)(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { Bool() }.flip
val meta_req = (new FIFOIO) { new MetaArrayReq() }
@ -748,7 +748,7 @@ class ioHellaCache extends Bundle {
val xcpt = (new HellaCacheExceptions).asInput
}
class HellaCache()(implicit conf: Configuration) extends Component {
class HellaCache(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val cpu = (new ioHellaCache).flip
val mem = new ioTileLink

2
rocket/src/main/scala/tile.scala
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@ -5,7 +5,7 @@ import Node._
import Constants._
import uncore._
class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal)
class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal)
{
val io = new Bundle {
val tilelink = new ioTileLink

4
rocket/src/main/scala/top.scala
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@ -13,7 +13,7 @@ object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants
}
import DummyTopLevelConstants._
case class Configuration(ntiles: Int, co: CoherencePolicyWithUncached)
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached)
class Top extends Component
{
@ -24,7 +24,7 @@ class Top extends Component
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence
}
implicit val conf = Configuration(NTILES, co)
implicit val conf = RocketConfiguration(NTILES, co)
val io = new Bundle {
val debug = new ioDebug