riscv/rocket-chip
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Fold uncore constants into TileLinkConfiguration, update coherence API

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This commit is contained in:
Henry Cook 2013-08-02 14:54:16 -07:00
parent bef6c1db35
commit 4eaab214d2
7 changed files with 67 additions and 57 deletions
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2
rocket/src/main/scala/core.scala
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@ -7,7 +7,7 @@ import Util._
class RocketIO(implicit conf: RocketConfiguration) extends Bundle
{
val host = new HTIFIO(conf.lnConf.nClients)
val host = new HTIFIO(conf.tl.ln.nClients)
val imem = new CPUFrontendIO()(conf.icache)
val vimem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)

2
rocket/src/main/scala/dpath.scala
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@ -9,7 +9,7 @@ import uncore.constants.AddressConstants._
class Datapath(implicit conf: RocketConfiguration) extends Component
{
val io = new Bundle {
val host = new HTIFIO(conf.lnConf.nClients)
val host = new HTIFIO(conf.tl.ln.nClients)
val ctrl = (new CtrlDpathIO).flip
val dmem = new HellaCacheIO()(conf.dcache)
val ptw = (new DatapathPTWIO).flip

2
rocket/src/main/scala/dpath_util.scala
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@ -105,7 +105,7 @@ object PCR
class PCR(implicit conf: RocketConfiguration) extends Component
{
val io = new Bundle {
val host = new HTIFIO(conf.lnConf.nClients)
val host = new HTIFIO(conf.tl.ln.nClients)
val rw = new Bundle {
val addr = UFix(INPUT, log2Up(conf.nxpr))
val cmd = Bits(INPUT, PCR.SZ)

26
rocket/src/main/scala/htif.scala
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@ -44,13 +44,14 @@ class SCRIO extends Bundle
val wdata = Bits(OUTPUT, 64)
}
class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component with ClientCoherenceAgent
class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent
{
implicit val lnConf = conf.ln
implicit val (ln, co) = (conf.ln, conf.co)
val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client
val io = new Bundle {
val host = new HostIO(w)
val cpu = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients).flip }
val mem = new TileLinkIO()(conf.ln)
val cpu = Vec(nTiles) { new HTIFIO(nTiles).flip }
val mem = new TileLinkIO
val scr = new SCRIO
}
@ -91,7 +92,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
val pcr_coreid = addr(log2Up(conf.ln.nClients)-1+20+1,20)
val pcr_coreid = addr(log2Up(nTiles)-1+20+1,20)
val pcr_wdata = packet_ram(0)
val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
@ -126,8 +127,8 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(9) { UFix() }
val state = Reg(resetVal = state_rx)
val rx_cmd = Mux(rx_word_count === UFix(0), next_cmd, cmd)
when (state === state_rx && rx_done) {
val rx_cmd = Mux(rx_word_count === UFix(0), next_cmd, cmd)
state := Mux(rx_cmd === cmd_readmem || rx_cmd === cmd_writemem, state_mem_req,
Mux(rx_cmd === cmd_readcr || rx_cmd === cmd_writecr, state_pcr_req,
state_tx))
@ -182,9 +183,10 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
}
x_init.io.enq.valid := state === state_mem_req
val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
val co = conf.co.asInstanceOf[CoherencePolicyWithUncached]
x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteAcquire(init_addr, UFix(0)), co.getUncachedReadAcquire(init_addr, UFix(0)))
io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UFix(conf.ln.nClients), UFix(0))
x_init.io.enq.bits := Mux(cmd === cmd_writemem,
Acquire(co.getUncachedWriteAcquireType, init_addr, UFix(0)),
Acquire(co.getUncachedReadAcquireType, init_addr, UFix(0)))
io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UFix(conf.ln.nClients), UFix(0)) // By convention HTIF is the client with the largest id
io.mem.acquire.data.valid := state === state_mem_wdata
io.mem.acquire.data.bits.payload.data := mem_req_data
io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack
@ -195,7 +197,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
io.mem.release.data.valid := Bool(false)
val pcrReadData = Reg{Bits(width = io.cpu(0).pcr_rep.bits.getWidth)}
for (i <- 0 until conf.ln.nClients) {
for (i <- 0 until nTiles) {
val my_reset = Reg(resetVal = Bool(true))
val my_ipi = Reg(resetVal = Bool(false))
@ -212,7 +214,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
}
cpu.ipi_rep.valid := my_ipi
cpu.ipi_req.ready := Bool(true)
for (j <- 0 until conf.ln.nClients) {
for (j <- 0 until nTiles) {
when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
my_ipi := Bool(true)
}
@ -239,7 +241,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w
val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)}
for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i)
scr_rdata(0) := conf.ln.nClients
scr_rdata(0) := nTiles
scr_rdata(1) := (UFix(REFILL_CYCLES*MEM_DATA_BITS/8) << x_init.io.enq.bits.addr.getWidth) >> 20
io.scr.wen := false

13
rocket/src/main/scala/icache.scala
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@ -4,7 +4,7 @@ import Chisel._
import uncore._
import Util._
case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
case class ICacheConfig(sets: Int, assoc: Int,
ntlb: Int = 8, nbtb: Int = 8,
code: Code = new IdentityCode)
{
@ -48,7 +48,7 @@ class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
val invalidate = Bool(OUTPUT)
}
class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) extends Component
class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Component
{
val io = new Bundle {
val cpu = new CPUFrontendIO()(c).flip
@ -121,8 +121,9 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
}
class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) extends Component
class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Component
{
implicit val lnConf = tl.ln
val io = new Bundle {
val req = new PipeIO()(new Bundle {
val idx = UFix(width = PGIDX_BITS)
@ -172,7 +173,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val s2_miss = s2_valid && !s2_any_tag_hit
rdy := state === s_ready && !s2_miss
//assert(!c.co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.")
//assert(!co.isVoluntary(io.mem.grant.bits.payload) || !io.mem.grant.valid, "UncachedRequestors shouldn't get voluntary grants.")
val (rf_cnt, refill_done) = Counter(io.mem.grant.valid, REFILL_CYCLES)
val repl_way = if (c.dm) UFix(0) else LFSR16(s2_miss)(log2Up(c.assoc)-1,0)
@ -241,13 +242,13 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
val finish_q = (new Queue(1)) { new GrantAck }
finish_q.io.enq.valid := refill_done && c.co.requiresAck(io.mem.grant.bits.payload)
finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload)
finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
// output signals
io.resp.valid := s2_hit
io.mem.acquire.meta.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.acquire.meta.bits.payload := c.co.getUncachedReadAcquire(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.acquire.meta.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UFix(c.offbits), UFix(0))
io.mem.acquire.data.valid := Bool(false)
io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq)
io.mem.grant.ready := Bool(true)

67
rocket/src/main/scala/nbdcache.scala
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@ -4,12 +4,14 @@ import Chisel._
import uncore._
import Util._
case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
case class DCacheConfig(sets: Int, ways: Int,
nmshr: Int, nrpq: Int, nsdq: Int, ntlb: Int,
states: Int = 2,
code: Code = new IdentityCode,
narrowRead: Boolean = true,
reqtagbits: Int = -1, databits: Int = -1)
{
require(states > 0)
require(OFFSET_BITS == log2Up(CACHE_DATA_SIZE_IN_BYTES))
require(OFFSET_BITS <= ACQUIRE_WRITE_MASK_BITS)
require(log2Up(OFFSET_BITS) <= ACQUIRE_SUBWORD_ADDR_BITS)
@ -32,7 +34,7 @@ case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
def databytes = databits/8
def wordoffbits = log2Up(databytes)
def isNarrowRead = narrowRead && databits*ways % MEM_DATA_BITS == 0
val statebits = 2 // TODO: obtain from coherence policy
val statebits = log2Up(states)
val metabits = statebits + tagbits
val encdatabits = code.width(databits)
val encmetabits = code.width(metabits)
@ -126,18 +128,18 @@ class DataWriteReq(implicit conf: DCacheConfig) extends Bundle {
override def clone = new DataWriteReq().asInstanceOf[this.type]
}
class InternalProbe(implicit conf: DCacheConfig) extends Probe {
val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS)
class InternalProbe(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Probe {
val client_xact_id = Bits(width = tl.clientXactIdBits)
override def clone = new InternalProbe().asInstanceOf[this.type]
}
class WritebackReq(implicit conf: DCacheConfig) extends Bundle {
class WritebackReq(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Bundle {
val tag = Bits(width = conf.tagbits)
val idx = Bits(width = conf.idxbits)
val way_en = Bits(width = conf.ways)
val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS)
val r_type = UFix(width = RELEASE_TYPE_MAX_BITS)
val client_xact_id = Bits(width = tl.clientXactIdBits)
val r_type = UFix(width = tl.co.releaseTypeBits)
override def clone = new WritebackReq().asInstanceOf[this.type]
}
@ -171,7 +173,8 @@ class MetaWriteReq(implicit conf: DCacheConfig) extends Bundle {
override def clone = new MetaWriteReq().asInstanceOf[this.type]
}
class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component {
class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Component {
implicit val ln = tl.ln
val io = new Bundle {
val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT)
@ -206,7 +209,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
val req_cmd = io.req_bits.cmd
val req_idx = req.addr(conf.untagbits-1,conf.offbits)
val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits)
val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !tl.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UFix(id)
val refill_done = reply && refill_count.andR
@ -232,7 +235,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
when (refill_done) { state := s_meta_write_req }
when (reply) {
refill_count := refill_count + UFix(1)
line_state := conf.co.newStateOnGrant(io.mem_grant.bits.payload, io.mem_req.bits)
line_state := tl.co.newStateOnGrant(io.mem_grant.bits.payload, io.mem_req.bits)
}
}
when (io.mem_req.fire()) { // s_refill_req
@ -249,29 +252,29 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
}
when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
acquire_type := conf.co.getAcquireTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
acquire_type := tl.co.getAcquireTypeOnSecondaryMiss(req_cmd, tl.co.newStateOnFlush(), io.mem_req.bits)
}
when (io.req_pri_val && io.req_pri_rdy) {
line_state := conf.co.newStateOnFlush()
line_state := tl.co.newStateOnFlush()
refill_count := UFix(0)
acquire_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
release_type := conf.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
acquire_type := tl.co.getAcquireTypeOnPrimaryMiss(req_cmd, tl.co.newStateOnFlush())
release_type := tl.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
req := io.req_bits
when (io.req_bits.tag_match) {
when (conf.co.isHit(req_cmd, io.req_bits.old_meta.state)) { // set dirty bit
when (tl.co.isHit(req_cmd, io.req_bits.old_meta.state)) { // set dirty bit
state := s_meta_write_req
line_state := conf.co.newStateOnHit(req_cmd, io.req_bits.old_meta.state)
line_state := tl.co.newStateOnHit(req_cmd, io.req_bits.old_meta.state)
}.otherwise { // upgrade permissions
state := s_refill_req
}
}.otherwise { // writback if necessary and refill
state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_meta_clear)
state := Mux(tl.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_meta_clear)
}
}
val ackq = (new Queue(1)) { (new LogicalNetworkIO){new GrantAck} }
ackq.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_grant.bits.payload)
ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAck(io.mem_grant.bits.payload)
ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
@ -293,7 +296,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
io.meta_write.valid := state === s_meta_write_req || state === s_meta_clear
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.state := Mux(state === s_meta_clear, conf.co.newStateOnFlush(), line_state)
io.meta_write.bits.data.state := Mux(state === s_meta_clear, tl.co.newStateOnFlush(), line_state)
io.meta_write.bits.data.tag := io.tag
io.meta_write.bits.way_en := req.way_en
@ -302,7 +305,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
io.wb_req.bits.idx := req_idx
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.client_xact_id := Bits(id)
io.wb_req.bits.r_type := conf.co.getReleaseTypeOnVoluntaryWriteback()
io.wb_req.bits.r_type := tl.co.getReleaseTypeOnVoluntaryWriteback()
io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
io.mem_req.bits.a_type := acquire_type
@ -325,7 +328,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
}
}
class MSHRFile(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component {
class MSHRFile(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Component {
implicit val ln = tl.ln
val io = new Bundle {
val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT)
@ -426,7 +430,7 @@ class MSHRFile(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration)
}
class WritebackUnit(implicit conf: DCacheConfig) extends Component {
class WritebackUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new WritebackReq() }.flip
val probe = (new FIFOIO) { new WritebackReq() }.flip
@ -498,7 +502,7 @@ class WritebackUnit(implicit conf: DCacheConfig) extends Component {
io.meta_read.bits.addr := io.release.bits.addr << conf.offbits
}
class ProbeUnit(implicit conf: DCacheConfig) extends Component {
class ProbeUnit(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new InternalProbe }.flip
val rep = (new FIFOIO) { new Release }
@ -529,7 +533,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
when (state === s_release && io.rep.ready) {
state := s_invalid
when (hit) {
state := Mux(conf.co.needsWriteback(line_state), s_writeback_req, s_meta_write)
state := Mux(tl.co.needsWriteback(line_state), s_writeback_req, s_meta_write)
}
}
when (state === s_mshr_req) {
@ -554,7 +558,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
io.req.ready := state === s_invalid
io.rep.valid := state === s_release
io.rep.bits := conf.co.newRelease(req, Mux(hit, line_state, conf.co.newStateOnFlush), req.client_xact_id)
io.rep.bits := Release(tl.co.getReleaseTypeOnProbe(req, Mux(hit, line_state, tl.co.newStateOnFlush)), req.addr, req.client_xact_id, req.master_xact_id)
io.meta_read.valid := state === s_meta_read
io.meta_read.bits.addr := req.addr << UFix(conf.offbits)
@ -562,7 +566,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
io.meta_write.valid := state === s_meta_write
io.meta_write.bits.way_en := way_en
io.meta_write.bits.idx := req.addr
io.meta_write.bits.data.state := conf.co.newStateOnProbe(req, line_state)
io.meta_write.bits.data.state := tl.co.newStateOnProbe(req, line_state)
io.meta_write.bits.data.tag := req.addr >> UFix(conf.idxbits)
io.wb_req.valid := state === s_writeback_req
@ -573,7 +577,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
io.wb_req.bits.client_xact_id := UFix(0) // DNC
}
class MetaDataArray(implicit conf: DCacheConfig) extends Component {
class MetaDataArray(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Component {
val io = new Bundle {
val read = (new FIFOIO) { new MetaReadReq }.flip
val write = (new FIFOIO) { new MetaWriteReq }.flip
@ -589,7 +593,7 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Component {
when (rst || io.write.valid) {
val addr = Mux(rst, rst_cnt, io.write.bits.idx)
val data = Cat(Mux(rst, conf.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag)
val data = Cat(Mux(rst, tl.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag)
val mask = Mux(rst, Fix(-1), io.write.bits.way_en)
tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
}
@ -735,7 +739,8 @@ class HellaCacheIO(implicit conf: DCacheConfig) extends Bundle {
val ptw = (new TLBPTWIO).flip
}
class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component {
class HellaCache(implicit conf: DCacheConfig, tl: TileLinkConfiguration) extends Component {
implicit val ln = tl.ln
val io = new Bundle {
val cpu = (new HellaCacheIO).flip
val mem = new TileLinkIO
@ -862,13 +867,13 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
// tag check and way muxing
def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(f)){gen}
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)){Bits()}.toBits
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && conf.co.isValid(meta.io.resp(w).state)){Bits()}.toBits
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && tl.co.isValid(meta.io.resp(w).state)){Bits()}.toBits
s1_clk_en := metaReadArb.io.out.valid
val s1_writeback = s1_clk_en && !s1_valid && !s1_replay
val s2_tag_match_way = RegEn(s1_tag_match_way, s1_clk_en)
val s2_tag_match = s2_tag_match_way.orR
val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEn(meta.io.resp(w).state, s1_clk_en)){Bits()})
val s2_hit = s2_tag_match && conf.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === conf.co.newStateOnHit(s2_req.cmd, s2_hit_state)
val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.newStateOnHit(s2_req.cmd, s2_hit_state)
// load-reserved/store-conditional
val lrsc_count = Reg(resetVal = UFix(0))

12
rocket/src/main/scala/tile.scala
View File

@ -4,7 +4,7 @@ import Chisel._
import uncore._
import Util._
case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: CoherencePolicyWithUncached,
case class RocketConfiguration(tl: TileLinkConfiguration,
icache: ICacheConfig, dcache: DCacheConfig,
fpu: Boolean, vec: Boolean,
fastLoadWord: Boolean = true,
@ -26,7 +26,9 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
val icachePortId = 1
val vicachePortId = 2
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
implicit val lnConf = confIn.lnConf
implicit val icConf = confIn.icache
implicit val tlConf = confIn.tl
implicit val lnConf = confIn.tl.ln
implicit val conf = confIn.copy(dcache = dcConf)
val io = new Bundle {
@ -35,10 +37,10 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
}
val core = new Core
val icache = new Frontend()(confIn.icache, lnConf)
val icache = new Frontend
val dcache = new HellaCache
val arbiter = new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts, confIn.dcache.co)
val arbiter = new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts)
arbiter.io.in(dcachePortId) <> dcache.io.mem
arbiter.io.in(icachePortId) <> icache.io.mem
@ -61,7 +63,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
}*/
if (conf.vec) {
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
val vicache = new Frontend()(ICacheConfig(128, 1), tlConf) // 128 sets x 1 ways (8KB)
arbiter.io.in(vicachePortId) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}