riscv/rocket-chip
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removing wires

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This commit is contained in:
Huy Vo 2012-05-24 10:33:15 -07:00
parent 181b20d69c
commit 7408c9ab69
10 changed files with 42 additions and 42 deletions
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4
rocket/src/main/scala/arbiter.scala
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@ -26,12 +26,12 @@ class rocketMemArbiter(n: Int) extends Component {
xi_rdy = xi_rdy && !io.requestor(i).xact_init.valid
}
var xi_bits = Wire() { new TransactionInit }
var xi_bits = new TransactionInit
xi_bits := io.requestor(n-1).xact_init.bits
xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2up(n)))
for (i <- n-2 to 0 by -1)
{
var my_xi_bits = Wire() { new TransactionInit }
var my_xi_bits = new TransactionInit
my_xi_bits := io.requestor(i).xact_init.bits
my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2up(n)))

10
rocket/src/main/scala/coherence.scala
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@ -96,7 +96,7 @@ abstract class IncoherentPolicy extends CoherencePolicy {
// UNIMPLEMENTED
def newStateOnProbeRequest(incoming: ProbeRequest, state: UFix): Bits = state
def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
val reply = Wire() { new ProbeReply() }
val reply = new ProbeReply()
reply.p_type := UFix(0)
reply.global_xact_id := UFix(0)
reply
@ -209,7 +209,7 @@ class MICoherence extends CoherencePolicyWithUncached {
def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
val reply = Wire() { new ProbeReply() }
val reply = new ProbeReply()
val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
probeReqInvalidate -> probeRepInvalidateData,
probeReqCopy -> probeRepCopyData
@ -336,7 +336,7 @@ class MEICoherence extends CoherencePolicyWithUncached {
def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
val reply = Wire() { new ProbeReply() }
val reply = new ProbeReply()
val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
probeReqInvalidate -> probeRepInvalidateData,
probeReqDowngrade -> probeRepDowngradeData,
@ -475,7 +475,7 @@ class MSICoherence extends CoherencePolicyWithUncached {
def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
val reply = Wire() { new ProbeReply() }
val reply = new ProbeReply()
val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
probeReqInvalidate -> probeRepInvalidateData,
probeReqDowngrade -> probeRepDowngradeData,
@ -614,7 +614,7 @@ class MESICoherence extends CoherencePolicyWithUncached {
def getTransactionInitTypeOnWriteback(): Bits = getTransactionInitTypeOnCacheControl(M_INV)
def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
val reply = Wire() { new ProbeReply() }
val reply = new ProbeReply()
val with_data = MuxLookup(incoming.p_type, probeRepInvalidateData, Array(
probeReqInvalidate -> probeRepInvalidateData,
probeReqDowngrade -> probeRepDowngradeData,

6
rocket/src/main/scala/ctrl.scala
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@ -359,7 +359,7 @@ class rocketCtrl extends Component
val id_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
val id_reg_icmiss = Reg(resetVal = Bool(false));
val id_reg_replay = Reg(resetVal = Bool(false));
val id_load_use = Wire(){Bool()};
val id_load_use = Bool();
val ex_reg_br_type = Reg(){Bits()}
val ex_reg_btb_hit = Reg(){Bool()};
@ -418,8 +418,8 @@ class rocketCtrl extends Component
val wb_reg_fp_val = Reg(resetVal = Bool(false));
val wb_reg_fp_sboard_set = Reg(resetVal = Bool(false));
val take_pc = Wire(){Bool()}
val take_pc_wb = Wire(){Bool()}
val take_pc = Bool()
val take_pc_wb = Bool()
when (!io.dpath.stalld) {
when (io.dpath.killf) {

6
rocket/src/main/scala/dpath.scala
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@ -70,7 +70,7 @@ class rocketDpath extends Component
val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val ex_reg_ctrl_div_fn = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_wdata = Wire() { Bits() };
val ex_wdata = Bits();
// memory definitions
val mem_reg_pc = Reg() { UFix() };
@ -93,9 +93,9 @@ class rocketDpath extends Component
val wb_reg_raddr1 = Reg() { UFix() };
val wb_reg_raddr2 = Reg() { UFix() };
val wb_reg_ll_wb = Reg(resetVal = Bool(false));
val wb_wdata = Wire() { Bits() };
val wb_wdata = Bits();
val dmem_resp_replay = Wire() { Bool() }
val dmem_resp_replay = Bool()
val r_dmem_resp_replay = Reg(resetVal = Bool(false));
val r_dmem_fp_replay = Reg(resetVal = Bool(false));
val r_dmem_resp_waddr = Reg() { UFix() };

6
rocket/src/main/scala/dpath_util.scala
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@ -25,8 +25,8 @@ class rocketDpathBTB(entries: Int) extends Component
val repl_way = LFSR16(io.wen)(log2up(entries)-1,0) // TODO: pseudo-LRU
var hit_reduction = Bool(false)
val hit = Wire() { Bool() }
val update = Wire() { Bool() }
val hit = Bool()
val update = Bool()
var update_reduction = Bool(false)
val mux = (new Mux1H(entries)) { Bits(width = VADDR_BITS) }
@ -118,7 +118,7 @@ class rocketDpathPCR extends Component
val r_irq_timer = Reg(resetVal = Bool(false));
val r_irq_ipi = Reg(resetVal = Bool(true))
val rdata = Wire() { Bits() };
val rdata = Bits();
val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr)
io.host.pcr_rep.valid := io.host.pcr_req.valid && !io.r.en && !io.host.pcr_req.bits.rw

8
rocket/src/main/scala/fpu.scala
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@ -214,10 +214,10 @@ class rocketFPIntUnit extends Component
val d2i = hardfloat.recodedFloatNToAny(io.in1, io.rm, ~io.cmd(1,0), 52, 12, 64)
// output muxing
val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
val (out_s, exc_s) = (Bits(), Bits())
out_s := Cat(Fill(32, unrec_s(31)), unrec_s)
exc_s := Bits(0)
val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
val (out_d, exc_d) = (Bits(), Bits())
out_d := unrec_d
exc_d := Bits(0)
@ -292,10 +292,10 @@ class rocketFPUFastPipe extends Component
val minmax = Mux(isnan2 || !isnan1 && (min === lt), io.in1, io.in2)
// output muxing
val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
val (out_s, exc_s) = (Bits(), Bits())
out_s := Reg(hardfloat.floatNToRecodedFloatN(io.fromint, 23, 9))
exc_s := Bits(0)
val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
val (out_d, exc_d) = (Bits(), Bits())
out_d := Reg(hardfloat.floatNToRecodedFloatN(io.fromint, 52, 12))
exc_d := Bits(0)

4
rocket/src/main/scala/icache.scala
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@ -56,8 +56,8 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
val r_cpu_req_ppn = Reg { Bits() }
val r_cpu_req_val = Reg(resetVal = Bool(false));
val rdy = Wire() { Bool() }
val tag_hit = Wire() { Bool() }
val rdy = Bool()
val tag_hit = Bool()
when (io.cpu.req_val && rdy) {
r_cpu_req_val := Bool(true)

2
rocket/src/main/scala/nbdcache.scala
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@ -803,7 +803,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
val r_req_read = r_req_load || r_req_amo
val r_req_write = r_req_store || r_req_amo
val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
val nack_hit = Wire() { Bool() }
val nack_hit = Bool()
val wb = new WritebackUnit(co)
val prober = new ProbeUnit(co)

30
rocket/src/main/scala/uncore.scala
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@ -281,20 +281,20 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
{
val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _, co))
val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
val x_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_MAX_BITS)} }
val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
val busy_arr = Vec(NGLOBAL_XACTS){ Bool() }
val addr_arr = Vec(NGLOBAL_XACTS){ Bits(width=PADDR_BITS-OFFSET_BITS) }
val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=TILE_ID_BITS) }
val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=TILE_XACT_ID_BITS) }
val x_type_arr = Vec(NGLOBAL_XACTS){ Bits(width=X_INIT_TYPE_MAX_BITS) }
val sh_count_arr = Vec(NGLOBAL_XACTS){ Bits(width=TILE_ID_BITS) }
val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Wire(){Bool()} } }
val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Wire(){Bool()} } }
val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bits(width = TILE_ID_BITS)} }
val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() }
val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Bool()} }
val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Bool()} }
val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Bits(width = TILE_ID_BITS) }
val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() }
for( i <- 0 until NGLOBAL_XACTS) {
val t = trackerList(i).io
@ -410,13 +410,13 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
// Nack conflicting transaction init attempts
val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() }
val abort_state_arr = Vec(ntiles) { Reg(resetVal = s_idle) }
val want_to_abort_arr = Vec(ntiles) { Wire() { Bool()} }
val want_to_abort_arr = Vec(ntiles) { Bool() }
for( j <- 0 until ntiles ) {
val x_init = io.tiles(j).xact_init
val x_init_data = io.tiles(j).xact_init_data
val x_abort = io.tiles(j).xact_abort
val abort_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
val conflicts = Vec(NGLOBAL_XACTS) { Wire() { Bool() } }
val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
for( i <- 0 until NGLOBAL_XACTS) {
val t = trackerList(i).io
conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.address)

8
rocket/src/main/scala/util.scala
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@ -208,7 +208,7 @@ class RRArbiter[T <: Data](n: Int)(data: => T) extends Component {
last_grant := choose
}
val dvec = Vec(n) { Wire() { data } }
val dvec = Vec(n) { data }
(0 until n).map(i => dvec(i) := io.in(i).bits )
io.out.valid := foldR(io.in.map(_.valid))(_||_)
@ -226,8 +226,8 @@ class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {
val io = new ioLockingArbiter(n)(data)
val locked = Vec(n) { Reg(resetVal = Bool(false)) }
val any_lock_held = (locked.toBits & io.lock.toBits).orR
val valid_arr = Vec(n) { Wire() { Bool() } }
val bits_arr = Vec(n) { Wire() { data } }
val valid_arr = Vec(n) { Bool() }
val bits_arr = Vec(n) { data }
for(i <- 0 until n) {
valid_arr(i) := io.in(i).valid
bits_arr(i) := io.in(i).bits
@ -270,7 +270,7 @@ object PriorityEncoderOH
{
def apply(in: Bits): UFix = doApply(in, 0)
def doApply(in: Bits, n: Int = 0): UFix = {
val out = Vec(in.getWidth) { Wire() { Bool() } }
val out = Vec(in.getWidth) { Bool() }
var none_hot = Bool(true)
for (i <- 0 until in.getWidth) {
out(i) := none_hot && in(i)