riscv/rocket-chip
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Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.

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This commit is contained in:
Henry Cook 2013-03-20 14:05:12 -07:00
parent 6d2541aced
commit 273bd34091
5 changed files with 40 additions and 98 deletions
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54
rocket/src/main/scala/arbiter.scala
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@ -47,57 +47,3 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp
resp.bits.replay := io.mem.resp.bits.replay && tag_hit
}
}
class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }}
val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }}
val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }}
}
class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component {
val io = new Bundle {
val mem = new UncachedRequestorIO
val requestor = Vec(n) { new UncachedRequestorIO }.flip
}
var acq_bits = new Acquire
acq_bits := io.requestor(n-1).acquire.bits.payload
acq_bits.client_xact_id := Cat(io.requestor(n-1).acquire.bits.payload.client_xact_id, UFix(n-1, log2Up(n)))
for (i <- n-2 to 0 by -1)
{
var my_acq_bits = new Acquire
my_acq_bits := io.requestor(i).acquire.bits.payload
my_acq_bits.client_xact_id := Cat(io.requestor(i).acquire.bits.payload.client_xact_id, UFix(i, log2Up(n)))
acq_bits = Mux(io.requestor(i).acquire.valid, my_acq_bits, acq_bits)
}
io.mem.acquire.bits.payload := acq_bits
io.mem.acquire.valid := io.requestor.map(_.acquire.valid).reduce(_||_)
io.requestor(0).acquire.ready := io.mem.acquire.ready
for (i <- 1 until n)
io.requestor(i).acquire.ready := io.requestor(i-1).acquire.ready && !io.requestor(i-1).acquire.valid
var ga_bits = io.requestor(n-1).grant_ack.bits
for (i <- n-2 to 0 by -1)
ga_bits = Mux(io.requestor(i).grant_ack.valid, io.requestor(i).grant_ack.bits, ga_bits)
io.mem.grant_ack.bits := ga_bits
io.mem.grant_ack.valid := io.requestor.map(_.grant_ack.valid).reduce(_||_)
io.requestor(0).grant_ack.ready := io.mem.grant_ack.ready
for (i <- 1 until n)
io.requestor(i).grant_ack.ready := io.requestor(i-1).grant_ack.ready && !io.requestor(i-1).grant_ack.valid
io.mem.grant.ready := Bool(false)
for (i <- 0 until n)
{
val tag = io.mem.grant.bits.payload.client_xact_id
io.requestor(i).grant.valid := Bool(false)
when (tag(log2Up(n)-1,0) === UFix(i)) {
io.requestor(i).grant.valid := io.mem.grant.valid
io.mem.grant.ready := io.requestor(i).grant.ready
}
io.requestor(i).grant.bits := io.mem.grant.bits
io.requestor(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
}
}

18
rocket/src/main/scala/htif.scala
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@ -36,7 +36,7 @@ class HTIFIO(ntiles: Int) extends Bundle
val ipi_rep = (new FIFOIO) { Bool() }.flip
}
class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent
class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component with ClientCoherenceAgent
{
implicit val lnConf = conf.ln
val io = new Bundle {
@ -104,10 +104,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
val mem_acked = Reg(resetVal = Bool(false))
val mem_gxid = Reg() { Bits() }
val mem_gsrc = Reg() { UFix(width = conf.ln.idBits) }
val mem_needs_ack = Reg() { Bool() }
when (io.mem.grant.valid) {
mem_acked := Bool(true)
mem_gxid := io.mem.grant.bits.payload.master_xact_id
mem_gsrc := io.mem.grant.bits.header.src
mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload)
}
io.mem.grant.ready := Bool(true)
@ -173,26 +175,16 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
val co = conf.co.asInstanceOf[CoherencePolicyWithUncached]
x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteAcquire(init_addr, UFix(0)), co.getUncachedReadAcquire(init_addr, UFix(0)))
io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq)
io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UFix(conf.ln.nClients), UFix(0))
io.mem.acquire_data.valid:= state === state_mem_wdata
io.mem.acquire_data.bits.payload.data := mem_req_data
io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack
io.mem.grant_ack.bits.payload.master_xact_id := mem_gxid
io.mem.grant_ack.bits.header.dst := mem_gsrc
io.mem.probe.ready := Bool(false)
io.mem.release.valid := Bool(false)
io.mem.release_data.valid := Bool(false)
io.mem.acquire.bits.header.src := UFix(conf.ln.nClients)
io.mem.acquire.bits.header.dst := UFix(0)
io.mem.acquire_data.bits.header.src := UFix(conf.ln.nClients)
io.mem.acquire_data.bits.header.dst := UFix(0)
io.mem.release.bits.header.src := UFix(conf.ln.nClients)
io.mem.release.bits.header.dst := UFix(0)
io.mem.release_data.bits.header.src := UFix(conf.ln.nClients)
io.mem.release_data.bits.header.dst := UFix(0)
io.mem.grant_ack.bits.header.src := UFix(conf.ln.nClients)
io.mem.grant_ack.bits.header.dst := UFix(0)
val pcrReadData = Vec(conf.ln.nClients) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
for (i <- 0 until conf.ln.nClients) {
val my_reset = Reg(resetVal = Bool(true))

5
rocket/src/main/scala/icache.scala
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@ -54,7 +54,7 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex
{
val io = new Bundle {
val cpu = new CPUFrontendIO()(c).flip
val mem = new UncachedRequestorIO
val mem = new UncachedTileLinkIO
}
val btb = new rocketDpathBTB(c.nbtb)
@ -134,7 +134,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val datablock = Bits(width = c.databits)
})
val invalidate = Bool(INPUT)
val mem = new UncachedRequestorIO
val mem = new UncachedTileLinkIO
}
val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(4) { UFix() }
@ -246,6 +246,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
io.resp.valid := s2_hit
io.mem.acquire.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.acquire.bits.payload := c.co.getUncachedReadAcquire(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.acquire_data.valid := Bool(false)
io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq)
io.mem.grant.ready := Bool(true)

39
rocket/src/main/scala/nbdcache.scala
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@ -124,7 +124,7 @@ class DataWriteReq(implicit conf: DCacheConfig) extends Bundle {
}
class InternalProbe(implicit conf: DCacheConfig) extends Probe {
val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS)
override def clone = new InternalProbe().asInstanceOf[this.type]
}
@ -133,7 +133,7 @@ class WritebackReq(implicit conf: DCacheConfig) extends Bundle {
val tag = Bits(width = conf.tagbits)
val idx = Bits(width = conf.idxbits)
val way_en = Bits(width = conf.ways)
val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS)
val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS)
val r_type = UFix(width = RELEASE_TYPE_MAX_BITS)
override def clone = new WritebackReq().asInstanceOf[this.type]
@ -160,7 +160,7 @@ class MetaWriteReq(implicit conf: DCacheConfig) extends Bundle {
override def clone = new MetaWriteReq().asInstanceOf[this.type]
}
class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component {
val io = new Bundle {
val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT)
@ -178,8 +178,8 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
val meta_read = (new FIFOIO) { new MetaReadReq }
val meta_write = (new FIFOIO) { new MetaWriteReq }
val replay = (new FIFOIO) { new Replay() }
val mem_rep = (new PipeIO) { new Grant }.flip
val mem_finish = (new FIFOIO) { new GrantAck }
val mem_grant = (new PipeIO) { (new LogicalNetworkIO) {new Grant} }.flip
val mem_finish = (new FIFOIO) { (new LogicalNetworkIO) {new GrantAck} }
val wb_req = (new FIFOIO) { new WritebackReq }
val probe_writeback = (new FIFOIO) { Bool() }.flip
val probe_refill = (new FIFOIO) { Bool() }.flip
@ -199,7 +199,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits)
val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id)
val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UFix(id)
val refill_done = reply && refill_count.andR
val wb_done = reply && (state === s_wb_resp)
@ -209,9 +209,10 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
rpq.io.enq.bits.sdq_id := io.req_sdq_id
rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid
val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck }
finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits)
finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id
val finish_q = (new Queue(2 /* wb + refill */)) { (new LogicalNetworkIO){new GrantAck} }
finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_grant.bits.payload)
finish_q.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
finish_q.io.enq.bits.header.dst := io.mem_grant.bits.header.src
when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) {
state := s_invalid
@ -227,7 +228,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
when (refill_done) { state := s_meta_write_req }
when (reply) {
refill_count := refill_count + UFix(1)
line_state := conf.co.newStateOnGrant(io.mem_rep.bits, io.mem_req.bits)
line_state := conf.co.newStateOnGrant(io.mem_grant.bits.payload, io.mem_req.bits)
}
}
when (state === s_refill_req) {
@ -307,7 +308,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
}
}
class MSHRFile(implicit conf: DCacheConfig) extends Component {
class MSHRFile(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT)
@ -317,8 +318,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
val meta_read = (new FIFOIO) { new MetaReadReq }
val meta_write = (new FIFOIO) { new MetaWriteReq }
val replay = (new FIFOIO) { new Replay }
val mem_rep = (new PipeIO) { new Grant }.flip
val mem_finish = (new FIFOIO) { new GrantAck }
val mem_grant = (new PipeIO) { (new LogicalNetworkIO){new Grant} }.flip
val mem_finish = (new FIFOIO) { (new LogicalNetworkIO){new GrantAck} }
val wb_req = (new FIFOIO) { new WritebackReq }
val probe = (new FIFOIO) { new Bool() }.flip
@ -339,7 +340,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
val meta_read_arb = (new Arbiter(conf.nmshr)) { new MetaReadReq }
val meta_write_arb = (new Arbiter(conf.nmshr)) { new MetaWriteReq }
val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire }
val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck }
val mem_finish_arb = (new Arbiter(conf.nmshr)) { (new LogicalNetworkIO){new GrantAck} }
val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq }
val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() }
val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() }
@ -378,7 +379,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
mshr.io.probe_writeback.valid := io.probe.valid
mshr.io.probe_writeback.bits := wb_probe_match
mshr.io.mem_rep <> io.mem_rep
mshr.io.mem_grant <> io.mem_grant
memRespMux(i) := mshr.io.mem_resp
pri_rdy = pri_rdy || mshr.io.req_pri_rdy
@ -399,7 +400,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
io.secondary_miss := idx_match
io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id)
io.mem_resp := memRespMux(io.mem_grant.bits.payload.client_xact_id)
io.fence_rdy := !fence
io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
@ -911,8 +912,8 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
mshr.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
mshr.io.req.bits.data := s2_req.data
mshr.io.mem_rep.valid := io.mem.grant.fire()
mshr.io.mem_rep.bits := io.mem.grant.bits.payload
mshr.io.mem_grant.valid := io.mem.grant.fire()
mshr.io.mem_grant.bits := io.mem.grant.bits
when (mshr.io.req.fire()) { replacer.miss }
io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready
@ -1023,5 +1024,5 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
io.cpu.resp.bits.data_subword := loadgen.byte
io.cpu.resp.bits.store_data := s2_req.data
io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_finish)
io.mem.grant_ack <> mshr.io.mem_finish
}

22
rocket/src/main/scala/tile.scala
View File

@ -24,7 +24,9 @@ case class RocketConfiguration(lnConf: LogicalNetworkConfiguration, co: Coherenc
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
val dcachePortID = 0
val dcachePortId = 0
val icachePortId = 1
val vicachePortId = 2
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)
implicit val lnConf = confIn.lnConf
implicit val conf = confIn.copy(dcache = dcConf)
@ -38,24 +40,24 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
val icache = new Frontend()(confIn.icache, lnConf)
val dcache = new HellaCache
val arbiter = new MemArbiter(memPorts)
arbiter.io.requestor(dcachePortID) <> dcache.io.mem
arbiter.io.requestor(1) <> icache.io.mem
val arbiter = new UncachedTileLinkIOArbiter(memPorts)
arbiter.io.in(dcachePortId) <> dcache.io.mem
arbiter.io.in(icachePortId) <> icache.io.mem
io.tilelink.acquire <> arbiter.io.mem.acquire
io.tilelink.acquire_data <> dcache.io.mem.acquire_data
arbiter.io.mem.grant <> io.tilelink.grant
io.tilelink.grant_ack <> arbiter.io.mem.grant_ack
io.tilelink.acquire <> arbiter.io.out.acquire
io.tilelink.acquire_data <> arbiter.io.out.acquire_data
arbiter.io.out.grant <> io.tilelink.grant
io.tilelink.grant_ack <> arbiter.io.out.grant_ack
dcache.io.mem.probe <> io.tilelink.probe
io.tilelink.release_data <> dcache.io.mem.release_data
io.tilelink.release.valid := dcache.io.mem.release.valid
dcache.io.mem.release.ready := io.tilelink.release.ready
io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortID, log2Up(memPorts))) // Mimic client id extension done by MemArbiter for Acquires from either cache)
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
if (conf.vec) {
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
arbiter.io.in(vicachePortId) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}