cleanups supporting uncore hierarchy
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febd26f505
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2c2b3a7678
@ -248,7 +248,7 @@ class ICache(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Module
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val finish_q = Module(new Queue(new GrantAck, 1))
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finish_q.io.enq.valid := refill_done && tl.co.requiresAck(io.mem.grant.bits.payload)
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finish_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(io.mem.grant.bits.payload.g_type)
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finish_q.io.enq.bits.master_xact_id := io.mem.grant.bits.payload.master_xact_id
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// output signals
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@ -260,7 +260,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, tl: TileLinkConfiguration) exte
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}
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val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1))
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ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAck(io.mem_grant.bits.payload)
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ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
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ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
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ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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@ -686,12 +686,12 @@ class AMOALU(implicit conf: DCacheConfig) extends Module {
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class HellaCacheReq(implicit val conf: DCacheConfig) extends DCacheBundle {
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val kill = Bool()
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val typ = Bits(width = 3)
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val typ = Bits(width = MT_SZ)
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val phys = Bool()
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val addr = UInt(width = conf.maxaddrbits)
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val data = Bits(width = conf.databits)
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val tag = Bits(width = conf.reqtagbits)
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val cmd = Bits(width = 4)
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val cmd = Bits(width = M_SZ)
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}
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class HellaCacheResp(implicit val conf: DCacheConfig) extends DCacheBundle {
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@ -20,7 +20,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
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if (fastLoadByte) require(fastLoadWord)
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}
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
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class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal)
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{
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val memPorts = 2 // Number of ports to outer memory system from tile: 1 from I$, 1 from D$
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val dcachePortId = 0
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