Final parameter refactor
This commit is contained in:
Henry Cook
parent
2d6aafc32e
commit
b42a2ab40a
@ -5,13 +5,13 @@ import Util._
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import Node._
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import uncore._
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case object BTBEntries extends Field[Int]
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case object NBTBEntries extends Field[Int]
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case object NRAS extends Field[Int]
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abstract trait BTBParameters extends UsesParameters {
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val vaddrBits = params(VAddrBits)
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val matchBits = params(PgIdxBits)
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val entries = params(BTBEntries)
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val entries = params(NBTBEntries)
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val nRAS = params(NRAS)
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val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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@ -2,10 +2,34 @@ package rocket
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import Chisel._
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import Util._
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import uncore.HTIFIO
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import uncore._
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case object FPUParams extends Field[PF]
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case object BuildFPU extends Field[Option[() => FPU]]
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case object XprLen extends Field[Int]
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case object NMultXpr extends Field[Int]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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case object FastMulDiv extends Field[Boolean]
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case object CoreInstBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object CoreDCacheReqTagBits extends Field[Int]
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abstract trait CoreParameters extends UsesParameters {
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val xprLen = params(XprLen)
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val coreInstBits = params(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xprLen
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val coreDataBytes = coreDataBits/8
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val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
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val coreMaxAddrBits = math.max(params(PPNBits),params(VPNBits)+1) + params(PgIdxBits)
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if(params(FastLoadByte)) require(params(FastLoadWord))
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require(params(RetireWidth) == 1) // for now...
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}
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abstract class CoreBundle extends Bundle with CoreParameters
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abstract class CoreModule extends Module with CoreParameters
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class RocketIO extends Bundle
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{
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@ -16,19 +40,20 @@ class RocketIO extends Bundle
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val rocc = new RoCCInterface().flip
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}
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class Core extends Module
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class Core extends Module with CoreParameters
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{
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val io = new RocketIO
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val ctrl = Module(new Control)
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val dpath = Module(new Datapath)
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if (!params(BuildFPU).isEmpty) {
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val p = Some(params.alter(params(FPUParams)))
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val fpu = Module(params(BuildFPU).get())(p)
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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}
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//If so specified, build an FPU module and wire it in
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params(BuildFPU)
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.map { bf => Module(bf()) }
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.foreach { fpu =>
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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}
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ctrl.io.dpath <> dpath.io.ctrl
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dpath.io.host <> io.host
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@ -171,7 +171,7 @@ class Datapath extends Module
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io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(params(VAddrBits)-1,0)).toUInt
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io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
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require(io.dmem.req.bits.tag.getWidth >= 6)
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require(params(DcacheReqTagBits) >= 6)
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require(params(CoreDCacheReqTagBits) >= 6)
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// processor control regfile read
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val pcr = Module(new CSRFile)
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@ -4,29 +4,30 @@ import Chisel._
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import uncore._
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import Util._
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case object InstBytes extends Field[Int]
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case object NITLBEntries extends Field[Int]
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case object ECCCode extends Field[Option[Code]]
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abstract trait FrontendParameters extends CacheParameters {
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val instBytes = params(InstBytes)
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abstract trait L1CacheParameters extends CacheParameters with CoreParameters {
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val co = params(TLCoherence)
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val code = params(ECCCode)
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}
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val code = params(ECCCode).getOrElse(new IdentityCode)
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}
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abstract trait FrontendParameters extends L1CacheParameters
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abstract class FrontendBundle extends Bundle with FrontendParameters
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abstract class FrontendModule extends Module with FrontendParameters
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class FrontendReq extends FrontendBundle {
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val pc = UInt(width = vaddrBits+1)
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class FrontendReq extends CoreBundle {
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val pc = UInt(width = params(VAddrBits)+1)
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}
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class FrontendResp extends FrontendBundle {
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val pc = UInt(width = vaddrBits+1) // ID stage PC
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val data = Bits(width = instBytes*8)
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class FrontendResp extends CoreBundle {
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val pc = UInt(width = params(VAddrBits)+1) // ID stage PC
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val data = Bits(width = coreInstBits)
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val xcpt_ma = Bool()
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val xcpt_if = Bool()
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}
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class CPUFrontendIO extends FrontendBundle {
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class CPUFrontendIO extends CoreBundle {
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val req = Valid(new FrontendReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_resp = Valid(new BTBResp).flip
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@ -44,7 +45,7 @@ class Frontend extends FrontendModule
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val btb = Module(new BTB)
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val icache = Module(new ICache)
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val tlb = Module(new TLB(params(NTLBEntries)))
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val tlb = Module(new TLB(params(NITLBEntries)))
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val s1_pc_ = Reg(UInt())
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val s1_pc = s1_pc_ & SInt(-2) // discard LSB of PC (throughout the pipeline)
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@ -57,7 +58,7 @@ class Frontend extends FrontendModule
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val msb = vaddrBits-1
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val pcp4_0 = s1_pc + UInt(instBytes)
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val pcp4_0 = s1_pc + UInt(coreInstBytes)
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val pcp4 = Cat(s1_pc(msb) & pcp4_0(msb), pcp4_0(msb,0))
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val icmiss = s2_valid && !icache.io.resp.valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4)
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@ -82,7 +83,7 @@ class Frontend extends FrontendModule
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s2_valid := Bool(false)
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}
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btb.io.req := s1_pc & SInt(-instBytes)
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btb.io.req := s1_pc & SInt(-coreInstBytes)
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btb.io.update := io.cpu.btb_update
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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@ -102,9 +103,9 @@ class Frontend extends FrontendModule
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
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io.cpu.resp.bits.pc := s2_pc & SInt(-instBytes) // discard PC LSBs
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(instBytes)) << log2Up(instBytes*8))
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(instBytes)-1,0) != UInt(0)
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io.cpu.resp.bits.pc := s2_pc & SInt(-coreInstBytes) // discard PC LSBs
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io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits))
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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io.cpu.btb_resp.valid := s2_btb_resp_valid
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@ -118,7 +119,7 @@ class ICacheReq extends FrontendBundle {
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}
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class ICacheResp extends FrontendBundle {
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val data = Bits(width = instBytes*8)
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val data = Bits(width = coreInstBits)
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val datablock = Bits(width = rowBits)
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}
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@ -131,7 +132,7 @@ class ICache extends FrontendModule
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val mem = new UncachedTileLinkIO
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}
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(instBytes))
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require(isPow2(coreInstBytes))
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require(pgIdxBits >= untagBits)
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val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4)
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@ -249,7 +250,7 @@ class ICache extends FrontendModule
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// if s1_tag_match is critical, replace with partial tag check
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when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s2_dout(i) := data_array(s1_raddr) }
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}
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val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(rowBytes)-1,log2Up(instBytes)) << log2Up(instBytes*8)))(instBytes*8-1,0))
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val s2_dout_word = s2_dout.map(x => (x >> (s2_offset(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits)))(coreInstBits-1,0))
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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@ -9,12 +9,12 @@ class MultiplierReq extends Bundle {
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val dw = Bits(width = SZ_DW)
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val in1 = Bits(width = params(XprLen))
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val in2 = Bits(width = params(XprLen))
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val tag = UInt(width = params(NXprBits))
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val tag = UInt(width = log2Up(params(NMultXpr)))
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}
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class MultiplierResp extends Bundle {
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val data = Bits(width = params(XprLen))
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val tag = UInt(width = params(NXprBits))
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val tag = UInt(width = log2Up(params(NMultXpr)))
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}
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class MultiplierIO extends Bundle {
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@ -7,25 +7,14 @@ import Util._
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case object StoreDataQueueDepth extends Field[Int]
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case object ReplayQueueDepth extends Field[Int]
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case object NMSHRs extends Field[Int]
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case object CoreReqTagBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object LRSCCycles extends Field[Int]
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//TODO PARAMS Also used by icache: is this ok?:
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case object NTLBEntries extends Field[Int]
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case object ECCCode extends Field[Code]
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case object NDTLBEntries extends Field[Int]
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abstract trait L1HellaCacheParameters extends CacheParameters {
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abstract trait L1HellaCacheParameters extends L1CacheParameters {
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val indexmsb = untagBits-1
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val indexlsb = blockOffBits
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val offsetmsb = indexlsb-1
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val offsetlsb = wordOffBits
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val co = params(TLCoherence)
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val code = params(ECCCode)
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val coreReqTagBits = params(CoreReqTagBits)
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val coreDataBits = params(CoreDataBits)
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val maxAddrBits = math.max(params(PPNBits),params(VPNBits)+1) + params(PgIdxBits)
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val coreDataBytes = coreDataBits/8
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val doNarrowRead = coreDataBits * nWays % rowBits == 0
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val encDataBits = code.width(coreDataBits)
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val encRowBits = encDataBits*rowWords
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@ -66,26 +55,26 @@ class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool)
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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}
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class HellaCacheReq extends L1HellaCacheBundle {
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class HellaCacheReq extends CoreBundle {
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val kill = Bool()
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val typ = Bits(width = MT_SZ)
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val phys = Bool()
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val addr = UInt(width = maxAddrBits)
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val addr = UInt(width = coreMaxAddrBits)
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val data = Bits(width = coreDataBits)
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val tag = Bits(width = coreReqTagBits)
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val tag = Bits(width = coreDCacheReqTagBits)
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val cmd = Bits(width = M_SZ)
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}
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class HellaCacheResp extends L1HellaCacheBundle {
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class HellaCacheResp extends CoreBundle {
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val nack = Bool() // comes 2 cycles after req.fire
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val replay = Bool()
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val typ = Bits(width = 3)
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val has_data = Bool()
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val data = Bits(width = coreDataBits)
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val data_subword = Bits(width = coreDataBits)
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val tag = Bits(width = coreReqTagBits)
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val tag = Bits(width = coreDCacheReqTagBits)
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val cmd = Bits(width = 4)
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val addr = UInt(width = maxAddrBits)
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val addr = UInt(width = coreMaxAddrBits)
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val store_data = Bits(width = coreDataBits)
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}
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@ -100,22 +89,22 @@ class HellaCacheExceptions extends Bundle {
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}
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// interface between D$ and processor/DTLB
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class HellaCacheIO extends L1HellaCacheBundle {
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class HellaCacheIO extends CoreBundle {
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val req = Decoupled(new HellaCacheReq)
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val resp = Valid(new HellaCacheResp).flip
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val replay_next = Valid(Bits(width = coreReqTagBits)).flip
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val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
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val xcpt = (new HellaCacheExceptions).asInput
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val ptw = new TLBPTWIO().flip
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val ordered = Bool(INPUT)
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}
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class MSHRReq extends HellaCacheReq {
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class MSHRReq extends HellaCacheReq with L1HellaCacheParameters {
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val tag_match = Bool()
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val old_meta = new L1Metadata
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val way_en = Bits(width = nWays)
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}
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class Replay extends HellaCacheReq {
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class Replay extends HellaCacheReq with L1HellaCacheParameters {
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val sdq_id = UInt(width = log2Up(params(StoreDataQueueDepth)))
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}
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@ -704,7 +693,7 @@ class HellaCache extends L1HellaCacheModule {
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val s1_sc = s1_req.cmd === M_XSC
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val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
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val dtlb = Module(new TLB(params(NTLBEntries)))
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val dtlb = Module(new TLB(params(NDTLBEntries)))
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dtlb.io.ptw <> io.cpu.ptw
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dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
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dtlb.io.req.bits.passthrough := s1_req.phys
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@ -4,44 +4,24 @@ import Chisel._
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import uncore._
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import Util._
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case object WhichL1Cache extends Field[String]
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case object NDCachePorts extends Field[Int]
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case object NTilePorts extends Field[Int]
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case object NPTWPorts extends Field[Int]
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case object BuildRoCC extends Field[Option[() => RoCC]]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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case object FastMulDiv extends Field[Boolean]
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case object DcacheReqTagBits extends Field[Int]
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case object XprLen extends Field[Int]
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case object NXpr extends Field[Int]
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case object NXprBits extends Field[Int]
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case object RocketDCacheParams extends Field[PF]
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case object RocketFrontendParams extends Field[PF]
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class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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if(params(FastLoadByte)) require(params(FastLoadWord))
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require(params(RetireWidth) == 1) // for now...
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val host = new HTIFIO
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}
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// Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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val optionalRoCC = params(BuildRoCC)
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val icache = Module(new Frontend, { case CacheName => "L1I" })
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val dcache = Module(new HellaCache, { case CacheName => "L1D" })
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val ptw = Module(new PTW(params(NPTWPorts)))
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val core = Module(new Core)
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val p = params.alter(params(RocketFrontendParams)) // Used in icache, Core
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val icache = Module(new Frontend)(p) //TODO PARAMS: best way to alter both?
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val p2 = params.alter(params(RocketDCacheParams)) // Used in dcache, PTW, RoCCm Core
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val dcache = Module(new HellaCache)(p2)
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val ptw = Module(new PTW(if(optionalRoCC.isEmpty) 2 else 5))(p2)
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// 2 ports, 1 from I$, 1 from D$, maybe 3 from RoCC
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val p3 = params.alter(params(RocketFrontendParams)).alter(params(RocketDCacheParams))
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val core = Module(new Core)(p3)
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val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))(p2)
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val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
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dcArb.io.requestor(0) <> ptw.io.mem
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dcArb.io.requestor(1) <> core.io.dmem
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dcArb.io.mem <> dcache.io.cpu
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@ -58,17 +38,19 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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memArb.io.in(dcPortId) <> dcache.io.mem
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memArb.io.in(1) <> icache.io.mem
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if(!optionalRoCC.isEmpty) {
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val rocc = Module(optionalRoCC.get())
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val dcIF = Module(new SimpleHellaCacheIF)
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dcIF.io.requestor <> rocc.io.mem
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core.io.rocc <> rocc.io
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dcArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(2) <> rocc.io.imem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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ptw.io.requestor(4) <> rocc.io.pptw
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}
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//If so specified, build an RoCC module and wire it in
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params(BuildRoCC)
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.map { br => Module(br()) }
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.foreach { rocc =>
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val dcIF = Module(new SimpleHellaCacheIF)
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dcIF.io.requestor <> rocc.io.mem
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core.io.rocc <> rocc.io
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dcArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(2) <> rocc.io.imem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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ptw.io.requestor(4) <> rocc.io.pptw
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}
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io.tilelink.acquire <> memArb.io.out.acquire
|
||||
io.tilelink.grant <> memArb.io.out.grant
|
||||
|
||||
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Reference in New Issue
Block a user