icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
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4d2e7172f6
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@ -80,8 +80,13 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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val mem_acked = Reg(resetVal = Bool(false))
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val mem_gxid = Reg() { Bits() }
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val mem_needs_ack = Reg() { Bool() }
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val mem_nacked = Reg(resetVal = Bool(false))
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when (io.mem.xact_rep.valid) { mem_acked := Bool(true); mem_gxid := io.mem.xact_rep.bits.global_xact_id }
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when (io.mem.xact_rep.valid) {
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mem_acked := Bool(true)
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mem_gxid := io.mem.xact_rep.bits.global_xact_id
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mem_needs_ack := io.mem.xact_rep.bits.require_ack
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}
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when (io.mem.xact_abort.valid) { mem_nacked := Bool(true) }
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val state_rx :: state_pcr :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(8) { UFix() }
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@ -152,7 +157,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3)
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io.mem.xact_init_data.valid:= state === state_mem_wdata
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io.mem.xact_init_data.bits.data := mem_req_data
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io.mem.xact_finish.valid := state === state_mem_finish
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io.mem.xact_finish.valid := (state === state_mem_finish) && mem_needs_ack
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io.mem.xact_finish.bits.global_xact_id := mem_gxid
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pcr_done := Bool(false)
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@ -127,7 +127,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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tag_hit := any_hit
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val finish_q = (new queue(1)) { new TransactionFinish }
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finish_q.io.enq.valid := refill_done
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finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.require_ack
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finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
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// output signals
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@ -46,7 +46,7 @@ class rocketIPrefetcher extends Component() {
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when (ip_mem_resp_val) { fill_cnt := fill_cnt + UFix(1) }
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val fill_done = fill_cnt.andR && ip_mem_resp_val
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finish_q.io.enq.valid := fill_done
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finish_q.io.enq.valid := fill_done && io.mem.xact_rep.bits.require_ack
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finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
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val forward = Reg(resetVal = Bool(false))
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@ -59,6 +59,7 @@ class rocketIPrefetcher extends Component() {
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forward && ip_mem_resp_abort
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io.icache.xact_rep.valid := io.mem.xact_rep.valid && !io.mem.xact_rep.bits.tile_xact_id(0) || (forward && pdq.io.deq.valid)
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io.icache.xact_rep.bits.data := Mux(forward, pdq.io.deq.bits, io.mem.xact_rep.bits.data)
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io.icache.xact_rep.bits.require_ack := !forward && io.mem.xact_rep.bits.require_ack
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pdq.io.flush := Reg(demand_miss && !hit || (state === s_bad_resp_wait), resetVal = Bool(false))
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pdq.io.enq.bits := io.mem.xact_rep.bits.data
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