riscv/rocket-chip
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Refactored packet headers/payloads

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This commit is contained in:
Henry Cook 2013-01-15 15:50:37 -08:00
parent e1225c5114
commit a2fa3fd04d
5 changed files with 51 additions and 50 deletions
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30
rocket/src/main/scala/arbiter.scala
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@ -48,32 +48,32 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp
}
}
class UncachedRequestorIO extends Bundle {
val xact_init = (new FIFOIO) { new TransactionInit }
val xact_abort = (new FIFOIO) { new TransactionAbort }.flip
val xact_rep = (new FIFOIO) { new TransactionReply }.flip
val xact_finish = (new FIFOIO) { new TransactionFinish }
class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val xact_init = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionInit }}
val xact_abort = (new MasterSourcedIO) {(new LogicalNetworkIO){new TransactionAbort }}
val xact_rep = (new MasterSourcedIO) {(new LogicalNetworkIO){new TransactionReply }}
val xact_finish = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionFinish }}
}
class MemArbiter(n: Int) extends Component {
class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component {
val io = new Bundle {
val mem = new UncachedRequestorIO
val requestor = Vec(n) { new UncachedRequestorIO }.flip
}
var xi_bits = new TransactionInit
xi_bits := io.requestor(n-1).xact_init.bits
xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2Up(n)))
xi_bits := io.requestor(n-1).xact_init.bits.payload
xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.payload.tile_xact_id, UFix(n-1, log2Up(n)))
for (i <- n-2 to 0 by -1)
{
var my_xi_bits = new TransactionInit
my_xi_bits := io.requestor(i).xact_init.bits
my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2Up(n)))
my_xi_bits := io.requestor(i).xact_init.bits.payload
my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.payload.tile_xact_id, UFix(i, log2Up(n)))
xi_bits = Mux(io.requestor(i).xact_init.valid, my_xi_bits, xi_bits)
}
io.mem.xact_init.bits := xi_bits
io.mem.xact_init.bits.payload := xi_bits
io.mem.xact_init.valid := io.requestor.map(_.xact_init.valid).reduce(_||_)
io.requestor(0).xact_init.ready := io.mem.xact_init.ready
for (i <- 1 until n)
@ -92,22 +92,22 @@ class MemArbiter(n: Int) extends Component {
io.mem.xact_rep.ready := Bool(false)
for (i <- 0 until n)
{
val tag = io.mem.xact_rep.bits.tile_xact_id
val tag = io.mem.xact_rep.bits.payload.tile_xact_id
io.requestor(i).xact_rep.valid := Bool(false)
when (tag(log2Up(n)-1,0) === UFix(i)) {
io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid
io.mem.xact_rep.ready := io.requestor(i).xact_rep.ready
}
io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits
io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2Up(n))
io.requestor(i).xact_rep.bits.payload.tile_xact_id := tag >> UFix(log2Up(n))
}
for (i <- 0 until n)
{
val tag = io.mem.xact_abort.bits.tile_xact_id
val tag = io.mem.xact_abort.bits.payload.tile_xact_id
io.requestor(i).xact_abort.valid := io.mem.xact_abort.valid && tag(log2Up(n)-1,0) === UFix(i)
io.requestor(i).xact_abort.bits := io.mem.xact_abort.bits
io.requestor(i).xact_abort.bits.tile_xact_id := tag >> UFix(log2Up(n))
io.requestor(i).xact_abort.bits.payload.tile_xact_id := tag >> UFix(log2Up(n))
}
io.mem.xact_abort.ready := Bool(true)

33
rocket/src/main/scala/htif.scala
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@ -38,6 +38,7 @@ class HTIFIO(ntiles: Int) extends Bundle
class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent
{
implicit val lnConf = conf.ln
val io = new Bundle {
val host = new HostIO(w)
val cpu = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles).flip }
@ -107,8 +108,8 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
val mem_nacked = Reg(resetVal = Bool(false))
when (io.mem.xact_rep.valid) {
mem_acked := Bool(true)
mem_gxid := io.mem.xact_rep.bits.global_xact_id
mem_needs_ack := io.mem.xact_rep.bits.require_ack
mem_gxid := io.mem.xact_rep.bits.payload.global_xact_id
mem_needs_ack := io.mem.xact_rep.bits.payload.require_ack
}
io.mem.xact_rep.ready := Bool(true)
when (io.mem.xact_abort.valid) { mem_nacked := Bool(true) }
@ -175,7 +176,7 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
for (i <- 0 until MEM_DATA_BITS/short_request_bits) {
val idx = Cat(mem_cnt, UFix(i, log2Up(MEM_DATA_BITS/short_request_bits)))
when (state === state_mem_rdata && io.mem.xact_rep.valid) {
packet_ram(idx) := io.mem.xact_rep.bits.data((i+1)*short_request_bits-1, i*short_request_bits)
packet_ram(idx) := io.mem.xact_rep.bits.payload.data((i+1)*short_request_bits-1, i*short_request_bits)
}
mem_req_data = Cat(packet_ram(idx), mem_req_data)
}
@ -183,25 +184,25 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
val co = conf.co.asInstanceOf[CoherencePolicyWithUncached]
x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0)))
io.mem.xact_init <> x_init.io.deq
io.mem.xact_init <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq)
io.mem.xact_init_data.valid:= state === state_mem_wdata
io.mem.xact_init_data.bits.data := mem_req_data
io.mem.xact_init_data.bits.payload.data := mem_req_data
io.mem.xact_finish.valid := (state === state_mem_finish) && mem_needs_ack
io.mem.xact_finish.bits.global_xact_id := mem_gxid
io.mem.xact_finish.bits.payload.global_xact_id := mem_gxid
io.mem.probe_req.ready := Bool(false)
io.mem.probe_rep.valid := Bool(false)
io.mem.probe_rep_data.valid := Bool(false)
io.mem.xact_init.header.src := UFix(1)
io.mem.xact_init.header.dst := UFix(0)
io.mem.xact_init_data.header.src := UFix(1)
io.mem.xact_init_data.header.dst := UFix(0)
io.mem.probe_rep.header.src := UFix(1)
io.mem.probe_rep.header.dst := UFix(0)
io.mem.probe_rep_data.header.src := UFix(1)
io.mem.probe_rep_data.header.dst := UFix(0)
io.mem.xact_finish.header.src := UFix(1)
io.mem.xact_finish.header.dst := UFix(0)
io.mem.xact_init.bits.header.src := UFix(conf.ln.nTiles)
io.mem.xact_init.bits.header.dst := UFix(0)
io.mem.xact_init_data.bits.header.src := UFix(conf.ln.nTiles)
io.mem.xact_init_data.bits.header.dst := UFix(0)
io.mem.probe_rep.bits.header.src := UFix(conf.ln.nTiles)
io.mem.probe_rep.bits.header.dst := UFix(0)
io.mem.probe_rep_data.bits.header.src := UFix(conf.ln.nTiles)
io.mem.probe_rep_data.bits.header.dst := UFix(0)
io.mem.xact_finish.bits.header.src := UFix(conf.ln.nTiles)
io.mem.xact_finish.bits.header.dst := UFix(0)
val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
for (i <- 0 until conf.ln.nTiles) {

14
rocket/src/main/scala/icache.scala
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@ -50,7 +50,7 @@ class CPUFrontendIO(implicit conf: ICacheConfig) extends Bundle {
val invalidate = Bool(OUTPUT)
}
class Frontend(implicit c: ICacheConfig) extends Component
class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) extends Component
{
val io = new Bundle {
val cpu = new CPUFrontendIO()(c).flip
@ -121,7 +121,7 @@ class Frontend(implicit c: ICacheConfig) extends Component
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
}
class ICache(implicit c: ICacheConfig) extends Component
class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) extends Component
{
val io = new Bundle {
val req = new PipeIO()(new Bundle {
@ -224,7 +224,7 @@ class ICache(implicit c: ICacheConfig) extends Component
val data_array = Mem(c.sets*REFILL_CYCLES, seqRead = true){ Bits(width = c.code.width(c.databits)) }
val s1_dout = Reg(){ Bits() }
when (io.mem.xact_rep.valid && repl_way === UFix(i)) {
val d = io.mem.xact_rep.bits.data
val d = io.mem.xact_rep.bits.payload.data
data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
}
/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
@ -238,14 +238,14 @@ class ICache(implicit c: ICacheConfig) extends Component
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
val finish_q = (new Queue(1)) { new TransactionFinish }
finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.require_ack
finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
finish_q.io.enq.valid := refill_done && io.mem.xact_rep.bits.payload.require_ack
finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.payload.global_xact_id
// output signals
io.resp.valid := s2_hit
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_finish <> finish_q.io.deq
io.mem.xact_init.bits.payload := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_finish <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq)
io.mem.xact_rep.ready := Bool(true)
// control state machine

20
rocket/src/main/scala/nbdcache.scala
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@ -915,9 +915,9 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
mshr.io.req.bits.data := s2_req.data
mshr.io.mem_rep.valid := io.mem.xact_rep.fire()
mshr.io.mem_rep.bits := io.mem.xact_rep.bits
mshr.io.mem_rep.bits := io.mem.xact_rep.bits.payload
mshr.io.mem_abort.valid := io.mem.xact_abort.valid
mshr.io.mem_abort.bits := io.mem.xact_abort.bits
mshr.io.mem_abort.bits := io.mem.xact_abort.bits.payload
io.mem.xact_abort.ready := Bool(true)
when (mshr.io.req.fire()) { replacer.miss }
@ -931,8 +931,8 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
metaWriteArb.io.in(0) <> mshr.io.meta_write
// probes
prober.io.req <> io.mem.probe_req
prober.io.rep <> io.mem.probe_rep
prober.io.req <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe_req)
FIFOedLogicalNetworkIOWrapper(prober.io.rep) <> io.mem.probe_rep
prober.io.mshr_req <> mshr.io.probe
prober.io.wb_req <> wb.io.probe
prober.io.way_en := s2_tag_match_way
@ -941,19 +941,19 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
prober.io.meta_write <> metaWriteArb.io.in(1)
// refills
val refill = conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits)
val refill = conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits.payload)
writeArb.io.in(1).valid := io.mem.xact_rep.valid && refill
io.mem.xact_rep.ready := writeArb.io.in(1).ready || !refill
writeArb.io.in(1).bits := mshr.io.mem_resp
writeArb.io.in(1).bits.wmask := Fix(-1)
writeArb.io.in(1).bits.data := io.mem.xact_rep.bits.data
writeArb.io.in(1).bits.data := io.mem.xact_rep.bits.payload.data
// writebacks
wb.io.req <> mshr.io.wb_req
wb.io.meta_read <> metaReadArb.io.in(3)
wb.io.data_req <> readArb.io.in(2)
wb.io.data_resp := s2_data_corrected
wb.io.probe_rep_data <> io.mem.probe_rep_data
FIFOedLogicalNetworkIOWrapper(wb.io.probe_rep_data) <> io.mem.probe_rep_data
// store->load bypassing
val s4_valid = Reg(s3_valid, resetVal = Bool(false))
@ -1021,8 +1021,8 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
xact_init_arb.io.in(1).valid := mshr.io.mem_req.valid && prober.io.req.ready
mshr.io.mem_req.ready := xact_init_arb.io.in(1).ready && prober.io.req.ready
xact_init_arb.io.in(1).bits := mshr.io.mem_req.bits
io.mem.xact_init <> xact_init_arb.io.out
io.mem.xact_init <> FIFOedLogicalNetworkIOWrapper(xact_init_arb.io.out)
io.mem.xact_init_data <> wb.io.mem_req_data
io.mem.xact_finish <> mshr.io.mem_finish
io.mem.xact_init_data <> FIFOedLogicalNetworkIOWrapper(wb.io.mem_req_data)
io.mem.xact_finish <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_finish)
}

4
rocket/src/main/scala/tile.scala
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@ -34,7 +34,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
}
val core = new Core
val icache = new Frontend()(confIn.icache)
val icache = new Frontend()(confIn.icache, lnConf)
val dcache = new HellaCache
val arbiter = new MemArbiter(memPorts)
@ -51,7 +51,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
io.tilelink.probe_rep_data <> dcache.io.mem.probe_rep_data
if (conf.vec) {
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co)) // 128 sets x 1 ways (8KB)
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}