riscv/rocket-chip
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refactor I$ config; remove Top class

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This commit is contained in:
Andrew Waterman 2012-11-04 16:59:36 -08:00
parent 7380c9fe60
commit e9eca6a95d
3 changed files with 10 additions and 106 deletions
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9
rocket/src/main/scala/icache.scala
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@ -6,7 +6,8 @@ import Constants._
import uncore._
import Util._
case class ICacheConfig(sets: Int, assoc: Int, parity: Boolean = false)
case class ICacheConfig(sets: Int, assoc: Int, co: CoherencePolicyWithUncached,
parity: Boolean = false)
{
val w = 1
val ibytes = INST_BITS/8
@ -50,7 +51,7 @@ class IOCPUFrontend extends Bundle {
val ptw = new IOTLBPTW().flip
}
class Frontend(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Component
class Frontend(c: ICacheConfig) extends Component
{
val io = new Bundle {
val cpu = new IOCPUFrontend().flip
@ -122,7 +123,7 @@ class Frontend(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Comp
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
}
class ICache(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Component
class ICache(c: ICacheConfig) extends Component
{
val io = new Bundle {
val req = new PipeIO()(new Bundle {
@ -246,7 +247,7 @@ class ICache(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Compon
// output signals
io.resp.valid := s2_hit
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_init.bits := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_finish <> finish_q.io.deq
// control state machine

7
rocket/src/main/scala/tile.scala
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@ -5,6 +5,9 @@ import Node._
import Constants._
import uncore._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
icache: ICacheConfig)
class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal)
{
val io = new Bundle {
@ -13,7 +16,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
}
val cpu = new rocketProc
val icache = new Frontend(ICacheConfig(4, 1)) // 128 sets x 4 ways (32KB)
val icache = new Frontend(conf.icache)
val dcache = new HellaCache
val arbiter = new rocketMemArbiter(DMEM_PORTS)
@ -31,7 +34,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
if (HAVE_VEC)
{
val vicache = new Frontend(ICacheConfig(128, 1)) // 128 sets x 1 ways (8KB)
val vicache = new Frontend(ICacheConfig(128, 1, conf.co)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}

100
rocket/src/main/scala/top.scala
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@ -1,100 +0,0 @@
package rocket
import Chisel._
import Node._
import Constants._
import uncore._
import collection.mutable.ArrayBuffer
object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
val NTILES = 1
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
}
import DummyTopLevelConstants._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached)
class Top extends Component
{
val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence
} else {
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence
}
implicit val rconf = RocketConfiguration(NTILES, co)
implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1, co)
val io = new Bundle {
val debug = new ioDebug
val host = new ioHost(16)
val mem = new ioMemPipe
}
val htif = new rocketHTIF(io.host.w)
val hub = new CoherenceHubBroadcast
hub.io.tiles(NTILES) <> htif.io.mem
io.host <> htif.io.host
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
io.mem.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
hub.io.mem.resp <> Pipe(io.mem.resp)
Assert(hub.io.mem.resp.ready, "hub.io.mem.resp.ready")
var error_mode = Bool(false)
for (i <- 0 until NTILES) {
val hl = htif.io.cpu(i)
val tl = hub.io.tiles(i)
val tile = new Tile(resetSignal = hl.reset)
tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
tl.xact_init <> Queue(tile.io.tilelink.xact_init)
tl.xact_init_data <> Queue(tile.io.tilelink.xact_init_data)
tile.io.tilelink.xact_abort <> Queue(tl.xact_abort)
tile.io.tilelink.xact_rep <> Queue(tl.xact_rep, 1, pipe = true)
tl.xact_finish <> Queue(tile.io.tilelink.xact_finish)
tile.io.tilelink.probe_req <> Queue(tl.probe_req)
tl.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1)
tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data)
tl.incoherent := hl.reset
}
io.debug.error_mode := error_mode
}
object top_main {
def main(args: Array[String]): Unit = {
val top = args(0)
val chiselArgs = ArrayBuffer[String]()
var i = 1
while (i < args.length) {
val arg = args(i)
arg match {
case "--NUM_PVFB" => {
hwacha.Constants.NUM_PVFB = args(i+1).toInt
i += 1
}
case "--WIDTH_PVFB" => {
hwacha.Constants.WIDTH_PVFB = args(i+1).toInt
hwacha.Constants.DEPTH_PVFB = args(i+1).toInt
i += 1
}
case "--CG" => {
hwacha.Constants.coarseGrained = true
}
case any => chiselArgs += arg
}
i += 1
}
chiselMain(chiselArgs.toArray, () => Class.forName(top).newInstance.asInstanceOf[Component])
}
}