Fixed bug regarding case sensitivity regarding ioICache,ioDCache

rocket/src/main/scala/arbiter.scala

@@ -20,8 +20,8 @@ class ioMem() extends Bundle
 
 class ioMemArbiter extends Bundle() {
   val mem = new ioMem();
-  val dcache = new ioDcache();
-//   val icache = new ioIcache();
+  val dcache = new ioDCache();
+//   val icache = new ioICache();
   val icache = new ioIPrefetcherMem().flip();
 }
 
@@ -35,10 +35,10 @@ class rocketMemArbiter extends Component {
   // Memory request is valid if either icache or dcache have a valid request
   io.mem.req_val := (io.icache.req_val || io.dcache.req_val);
 
-  // Set read/write bit.  Icache always reads
+  // Set read/write bit.  ICache always reads
   io.mem.req_rw := Mux(io.dcache.req_val, io.dcache.req_rw, Bool(false));
 
-  // Give priority to Icache
+  // Give priority to ICache
   io.mem.req_addr := Mux(io.dcache.req_val, io.dcache.req_addr, io.icache.req_addr);
 
   // low bit of tag=0 for I$, 1 for D$

rocket/src/main/scala/dcache.scala

@@ -28,7 +28,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
 }
 
 // interface between D$ and next level in memory hierarchy
-class ioDcache(view: List[String] = null) extends Bundle(view) {
+class ioDCache(view: List[String] = null) extends Bundle(view) {
   val req_addr  = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
   val req_tag   = UFix(DMEM_TAG_BITS, INPUT);
   val req_val   = Bool(INPUT);
@@ -42,12 +42,12 @@ class ioDcache(view: List[String] = null) extends Bundle(view) {
 
 class ioDCacheDM extends Bundle() {
   val cpu = new ioDmem();
-  val mem = new ioDcache().flip();
+  val mem = new ioDCache().flip();
 }
 
 class ioDCacheHella extends Bundle() {
   val cpu = new ioDmem();
-  val mem = new ioDcache().flip();
+  val mem = new ioDCache().flip();
 }
 
 class rocketDCacheStoreGen extends Component {

rocket/src/main/scala/icache.scala

@@ -18,7 +18,7 @@ class ioImem(view: List[String] = null) extends Bundle (view)
 }
 
 // interface between I$ and memory (128 bits wide)
-class ioIcache(view: List[String] = null) extends Bundle (view)
+class ioICache(view: List[String] = null) extends Bundle (view)
 {
   val req_addr  = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
   val req_val   = Bool(INPUT);
@@ -27,10 +27,10 @@ class ioIcache(view: List[String] = null) extends Bundle (view)
   val resp_val  = Bool(OUTPUT);
 }
 
-class ioICache extends Bundle()
+class ioRocketICache extends Bundle()
 {
   val cpu = new ioImem();
-  val mem = new ioIcache().flip();
+  val mem = new ioICache().flip();
 }
 
 // basic direct mapped instruction cache
@@ -38,7 +38,7 @@ class ioICache extends Bundle()
 // parameters :
 //    lines = # cache lines
 class rocketICache(sets: Int, assoc: Int) extends Component {
-  val io = new ioICache();
+  val io = new ioRocketICache();
 
   val lines = sets * assoc;
   val addrbits = PADDR_BITS;

rocket/src/main/scala/icache_prefetch.scala

@@ -17,7 +17,7 @@ class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
 }
 
 class ioIPrefetcher extends Bundle() {
-  val icache = new ioIcache();
+  val icache = new ioICache();
   val mem = new ioIPrefetcherMem();
 }