views removed

rocket/src/main/scala/ctrl.scala

@@ -75,7 +75,7 @@ class ioCtrlDpath extends Bundle()
 class ioCtrlAll extends Bundle()
 {
   val dpath   = new ioCtrlDpath();
-  val imem    = new ioImem(List("req_val", "resp_val")).flip
+  val imem    = new ioImem().flip
   val dmem = new ioHellaCache
   val dtlb_val = Bool(OUTPUT);
   val dtlb_kill = Bool(OUTPUT);

rocket/src/main/scala/htif.scala

@@ -4,12 +4,12 @@ import Chisel._
 import Node._;
 import Constants._;
 
-class ioDebug(view: List[String] = null) extends Bundle(view)
+class ioDebug extends Bundle
 {
   val error_mode  = Bool(OUTPUT);
 }
 
-class ioHost(w: Int, view: List[String] = null) extends Bundle(view)
+class ioHost(w: Int) extends Bundle
 {
   val in = new ioDecoupled()(Bits(width = w)).flip
   val out = new ioDecoupled()(Bits(width = w))

rocket/src/main/scala/icache.scala

@@ -6,7 +6,7 @@ import Constants._;
 import scala.math._;
 
 // interface between I$ and pipeline/ITLB (32 bits wide)
-class ioImem(view: List[String] = null) extends Bundle (view)
+class ioImem extends Bundle
 {
   val invalidate = Bool(INPUT);
   val itlb_miss  = Bool(INPUT);

rocket/src/main/scala/itlb.scala

@@ -87,7 +87,7 @@ class ioTLB_PTW extends Bundle
 }
 
 // interface between ITLB and fetch stage of pipeline
-class ioITLB_CPU(view: List[String] = null) extends Bundle(view)
+class ioITLB_CPU extends Bundle
 {
   // status bits (from PCR), to check current permission and whether VM is enabled
   val status = Bits(32, INPUT);