TileLinkIO.GrantAck -> TileLinkIO.Finish
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@ -271,7 +271,7 @@ class ICache(implicit c: ICacheConfig) extends Module
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io.resp.bits.data := Mux1H(s2_tag_hit, s2_dout_word)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val ack_q = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1))
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val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ack_q.io.enq.valid := refill_done && tl.co.requiresAckForGrant(refill_bits.payload.g_type)
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ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id
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ack_q.io.enq.bits.header.dst := refill_bits.header.src
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@ -280,7 +280,7 @@ class ICache(implicit c: ICacheConfig) extends Module
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io.resp.valid := s2_hit
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io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
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io.mem.acquire.bits.payload := Acquire(tl.co.getUncachedReadAcquireType, s2_addr >> UInt(c.offbits), UInt(0))
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io.mem.grant_ack <> ack_q.io.deq
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io.mem.finish <> ack_q.io.deq
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// control state machine
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switch (state) {
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@ -142,7 +142,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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val meta_write = Decoupled(new MetaWriteReq)
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val replay = Decoupled(new Replay)
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val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
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val mem_finish = Decoupled(new LogicalNetworkIO(new GrantAck))
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val mem_finish = Decoupled(new LogicalNetworkIO(new Finish))
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val wb_req = Decoupled(new WritebackReq)
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val probe_rdy = Bool(OUTPUT)
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}
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@ -224,7 +224,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Module {
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}
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}
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val ackq = Module(new Queue(new LogicalNetworkIO(new GrantAck), 1))
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val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ackq.io.enq.valid := (wb_done || refill_done) && tl.co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
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ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
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ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
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@ -292,7 +292,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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val meta_write = Decoupled(new MetaWriteReq)
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val replay = Decoupled(new Replay)
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val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip
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val mem_finish = Decoupled(new LogicalNetworkIO(new GrantAck))
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val mem_finish = Decoupled(new LogicalNetworkIO(new Finish))
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val wb_req = Decoupled(new WritebackReq)
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val probe_rdy = Bool(OUTPUT)
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@ -315,7 +315,7 @@ class MSHRFile(implicit conf: DCacheConfig) extends Module {
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val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, conf.nmshr))
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val meta_write_arb = Module(new Arbiter(new MetaWriteReq, conf.nmshr))
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val mem_req_arb = Module(new Arbiter(new Acquire, conf.nmshr))
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val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new GrantAck), conf.nmshr))
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val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), conf.nmshr))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, conf.nmshr))
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val replay_arb = Module(new Arbiter(new Replay, conf.nmshr))
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val alloc_arb = Module(new Arbiter(Bool(), conf.nmshr))
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@ -992,7 +992,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Module {
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io.cpu.replay_next.valid := s1_replay && (s1_read || s1_sc)
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io.cpu.replay_next.bits := s1_req.tag
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io.mem.grant_ack <> mshrs.io.mem_finish
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io.mem.finish <> mshrs.io.mem_finish
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}
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// exposes a sane decoupled request interface
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@ -75,7 +75,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module
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io.tilelink.acquire <> memArb.io.out.acquire
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memArb.io.out.grant <> io.tilelink.grant
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io.tilelink.grant_ack <> memArb.io.out.grant_ack
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io.tilelink.finish <> memArb.io.out.finish
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dcache.io.mem.probe <> io.tilelink.probe
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io.tilelink.release.valid := dcache.io.mem.release.valid
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dcache.io.mem.release.ready := io.tilelink.release.ready
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