Fixed btb/icache bugs regarding resp mask, fw==1
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91efdc379b
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08d2c13330
@ -79,7 +79,7 @@ class BHT(nbht: Int) {
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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// - "bridx" is the low-order PC bits of the predicted branch (after
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// shifting off the lowest log(inst_bytes) bits off).
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// shifting off the lowest log(inst_bytes) bits off).
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// - "resp.mask" provides a mask of valid instructions (instructions are
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// masked off by the predicted taken branch).
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class BTBUpdate extends Bundle with BTBParameters {
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@ -196,9 +196,9 @@ class BTB extends Module with BTBParameters {
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useRAS(waddr) := r_update.bits.isReturn
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isJump(waddr) := r_update.bits.isJump
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if (params(FetchWidth) == 1) {
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brIdx(waddr) := UInt(0)
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brIdx(waddr) := UInt(0)
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} else {
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brIdx(waddr) := r_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
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brIdx(waddr) := r_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
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}
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}
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@ -226,8 +226,14 @@ class BTB extends Module with BTBParameters {
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.entry := OHToUInt(hits)
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io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1))
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io.resp.bits.bridx := brIdx(io.resp.bits.entry)
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if (params(FetchWidth) == 1) {
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io.resp.bits.mask := UInt(1)
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} else {
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io.resp.bits.mask := Mux(io.resp.valid, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
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((UInt(1) << UInt(params(FetchWidth)))-UInt(1)))
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// val all_ones = UInt((1 << coreFetchWidth)-1)
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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@ -58,9 +58,10 @@ class Frontend extends FrontendModule
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val s2_xcpt_if = Reg(init=Bool(false))
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val msb = vaddrBits-1
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val lsb = log2Up(coreFetchWidth*coreInstBytes)
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val ntpc_0 = s1_pc + UInt(coreInstBytes)
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val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,0))
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val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
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val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
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val icmiss = s2_valid && !icache.io.resp.valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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@ -115,7 +116,8 @@ class Frontend extends FrontendModule
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val all_ones = UInt((1 << coreFetchWidth)-1)
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val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
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io.cpu.resp.bits.mask := msk_pc & btb.io.resp.bits.mask
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// TODO what is the best way to handle the clock-gating of s2_btb_resp_bits?
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io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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