remove aborts; simplify probes
This commit is contained in:
Andrew Waterman
parent
e0361840bd
commit
ea9d0b771e
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@ -50,7 +50,6 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp
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class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }}
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val abort = (new MasterSourcedIO) {(new LogicalNetworkIO){new Abort }}
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val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }}
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val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }}
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}
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@ -101,14 +100,4 @@ class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Com
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io.requestor(i).grant.bits := io.mem.grant.bits
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io.requestor(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
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}
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for (i <- 0 until n)
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{
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val tag = io.mem.abort.bits.payload.client_xact_id
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io.requestor(i).abort.valid := io.mem.abort.valid && tag(log2Up(n)-1,0) === UFix(i)
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io.requestor(i).abort.bits := io.mem.abort.bits
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io.requestor(i).abort.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
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}
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io.mem.abort.ready := Bool(true)
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}
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@ -105,15 +105,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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val mem_acked = Reg(resetVal = Bool(false))
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val mem_gxid = Reg() { Bits() }
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val mem_needs_ack = Reg() { Bool() }
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val mem_nacked = Reg(resetVal = Bool(false))
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when (io.mem.grant.valid) {
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mem_acked := Bool(true)
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mem_gxid := io.mem.grant.bits.payload.master_xact_id
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mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload)
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}
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io.mem.grant.ready := Bool(true)
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when (io.mem.abort.valid) { mem_nacked := Bool(true) }
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io.mem.abort.ready := Bool(true)
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val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(9) { UFix() }
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val state = Reg(resetVal = state_rx)
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@ -137,20 +134,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
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mem_cnt := mem_cnt + UFix(1)
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}
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when (state === state_mem_wresp) {
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when (mem_nacked) {
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state := state_mem_req
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mem_nacked := Bool(false)
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}
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when (mem_acked) {
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state := state_mem_finish
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mem_acked := Bool(false)
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}
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}
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when (state === state_mem_rdata) {
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when (mem_nacked) {
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state := state_mem_req
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mem_nacked := Bool(false)
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}
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when (io.mem.grant.valid) {
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when (mem_cnt.andR) {
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state := state_mem_finish
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@ -259,7 +259,6 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
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when (io.mem.acquire.ready && finish_q.io.enq.ready) { state := s_refill_wait }
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}
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is (s_refill_wait) {
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when (io.mem.abort.valid) { state := s_request }
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when (io.mem.grant.valid) { state := s_refill }
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}
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is (s_refill) {
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@ -178,11 +178,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val meta_read = (new FIFOIO) { new MetaReadReq }
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val meta_write = (new FIFOIO) { new MetaWriteReq }
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val replay = (new FIFOIO) { new Replay() }
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val mem_abort = (new PipeIO) { new Abort }.flip
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val mem_rep = (new PipeIO) { new Grant }.flip
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val mem_probe = (new PipeIO) { new Probe }.flip
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val mem_probe_ready = Bool(OUTPUT)
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val self_probe = (new FIFOIO) { new InternalProbe }
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val mem_finish = (new FIFOIO) { new GrantAck }
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val wb_req = (new FIFOIO) { new WritebackReq }
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val probe_writeback = (new FIFOIO) { Bool() }.flip
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@ -197,32 +193,16 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val line_state = Reg { UFix() }
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val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) }
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val req = Reg { new MSHRReq() }
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val sent_wb_req = Reg { Bool() }
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val req_cmd = io.req_bits.cmd
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val req_idx = req.addr(conf.untagbits-1,conf.offbits)
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val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits)
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val probe_idx_match = req_idx === io.mem_probe.bits.addr(conf.untagbits-1,conf.offbits)
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val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id)
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val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id)
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val refill_done = reply && refill_count.andR
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val wb_done = reply && (state === s_wb_resp)
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val probe_wb_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.old_meta.tag
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val probe_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.addr >> conf.untagbits
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val handle_probe = (state != s_invalid) && probe_idx_match
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val kill_probe = sent_wb_req && probe_wb_tag_match && conf.co.pendingVoluntaryReleaseIsSufficient(release_type, io.mem_probe.bits.p_type)
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val probe_q = (new Queue(1, pipe = true, flow = true)) { new Probe }
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probe_q.io.enq.valid := io.mem_probe.valid && handle_probe && sent_wb_req && !kill_probe
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io.mem_probe_ready := probe_q.io.enq.ready && handle_probe
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probe_q.io.enq.bits := io.mem_probe.bits
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io.self_probe.valid := probe_q.io.deq.valid && (state != s_wb_resp)
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probe_q.io.deq.ready := io.self_probe.ready && (state != s_wb_resp)
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io.self_probe.bits := probe_q.io.deq.bits
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io.self_probe.bits.client_xact_id := UFix(id)
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val rpq = (new Queue(conf.nrpq)) { new Replay }
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd)
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rpq.io.enq.bits := io.req_bits
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@ -232,7 +212,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck }
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finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits)
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finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id
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io.wb_req.valid := Bool(false)
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when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) {
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state := s_invalid
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@ -250,28 +229,18 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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refill_count := refill_count + UFix(1)
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line_state := conf.co.newStateOnGrant(io.mem_rep.bits, io.mem_req.bits)
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}
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when (abort) { state := s_refill_req }
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}
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when (state === s_refill_req) {
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when (abort) { state := s_refill_req }
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.elsewhen (io.mem_req.ready) { state := s_refill_resp }
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when (io.mem_req.ready) { state := s_refill_resp }
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}
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when (state === s_meta_clear && io.meta_write.ready) {
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state := s_refill_req
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}
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when (state === s_wb_resp) {
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when (reply) { state := s_meta_clear }
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when (abort) { state := s_wb_req }
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}
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when (state === s_wb_req) {
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io.wb_req.valid := Bool(true)
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when (io.probe_writeback.valid && idx_match) {
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io.wb_req.valid := Bool(false)
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when (io.probe_writeback.bits) { state := s_refill_req }
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}.elsewhen (io.wb_req.ready) {
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sent_wb_req := Bool(true)
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state := s_wb_resp
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}
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when (state === s_wb_req && io.wb_req.ready) {
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state := s_wb_resp
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}
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when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
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@ -283,7 +252,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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acquire_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
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release_type := conf.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
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req := io.req_bits
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sent_wb_req := Bool(false)
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state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_refill_req)
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when (io.req_bits.tag_match) {
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@ -297,7 +265,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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}
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io.idx_match := (state != s_invalid) && idx_match
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io.probe_idx_match := (state != s_invalid) && probe_idx_match
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io.mem_resp := req
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io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits
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io.tag := req.addr >> conf.untagbits
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@ -310,14 +277,15 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
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io.meta_write.bits.data.tag := io.tag
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io.meta_write.bits.way_en := req.way_en
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io.wb_req.valid := state === s_wb_req
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io.wb_req.bits.tag := req.old_meta.tag
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io.wb_req.bits.idx := req_idx
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io.wb_req.bits.way_en := req.way_en
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io.wb_req.bits.client_xact_id := Bits(id)
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io.wb_req.bits.r_type := conf.co.getReleaseTypeOnVoluntaryWriteback()
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io.probe_writeback.ready := (state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match
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io.probe_refill.ready := (state != s_refill_resp && state != s_drain_rpq) || !idx_match
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io.probe_writeback.ready := (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match
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io.probe_refill.ready := (state != s_refill_resp && state != s_meta_write_req && state != s_meta_write_resp && state != s_drain_rpq) || !idx_match
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io.mem_req.valid := state === s_refill_req
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io.mem_req.bits.a_type := acquire_type
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@ -349,12 +317,10 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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val meta_read = (new FIFOIO) { new MetaReadReq }
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val meta_write = (new FIFOIO) { new MetaWriteReq }
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val replay = (new FIFOIO) { new Replay }
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val mem_abort = (new PipeIO) { new Abort }.flip
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val mem_rep = (new PipeIO) { new Grant }.flip
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val mem_finish = (new FIFOIO) { new GrantAck }
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val wb_req = (new FIFOIO) { new WritebackReq }
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val mem_probe = (new FIFOIO) { new Probe }.flip
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val self_probe = (new FIFOIO) { new InternalProbe }
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val probe = (new FIFOIO) { new Bool() }.flip
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val fence_rdy = Bool(OUTPUT)
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}
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@ -375,7 +341,6 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire }
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val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck }
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val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq }
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val self_probe_arb = (new Arbiter(conf.nmshr+1)) { new InternalProbe }
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val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() }
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val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() }
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@ -383,18 +348,11 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.addr >> conf.untagbits
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var idx_match = Bool(false)
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var probe_idx_match = Bool(false)
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var pri_rdy = Bool(false)
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var fence = Bool(false)
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var sec_rdy = Bool(false)
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var writeback_probe_rdy = Bool(true)
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var refill_probe_rdy = Bool(true)
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var mem_probe_rdy = Bool(false)
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self_probe_arb.io.in(0).valid := io.mem_probe.valid && !probe_idx_match
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self_probe_arb.io.in(0).bits := io.mem_probe.bits
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self_probe_arb.io.in(0).bits.client_xact_id := UFix(0) // DNC
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mem_probe_rdy = mem_probe_rdy || self_probe_arb.io.in(0).ready
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for (i <- 0 to conf.nmshr-1) {
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val mshr = new MSHR(i)
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@ -410,19 +368,16 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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mshr.io.req_bits := io.req.bits
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mshr.io.req_sdq_id := sdq_alloc_id
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mshr.io.mem_probe <> io.mem_probe
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mshr.io.meta_read <> meta_read_arb.io.in(i)
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mshr.io.meta_write <> meta_write_arb.io.in(i)
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mshr.io.mem_req <> mem_req_arb.io.in(i)
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mshr.io.mem_finish <> mem_finish_arb.io.in(i)
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mshr.io.wb_req <> wb_req_arb.io.in(i)
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mshr.io.self_probe <> self_probe_arb.io.in(i+1)
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mshr.io.replay <> replay_arb.io.in(i)
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mshr.io.probe_refill.valid := io.mem_probe.valid && tag_match
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mshr.io.probe_writeback.valid := io.mem_probe.valid
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mshr.io.probe_refill.valid := io.probe.valid && tag_match
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mshr.io.probe_writeback.valid := io.probe.valid
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mshr.io.probe_writeback.bits := wb_probe_match
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mshr.io.mem_abort <> io.mem_abort
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mshr.io.mem_rep <> io.mem_rep
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memRespMux(i) := mshr.io.mem_resp
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@ -430,10 +385,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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sec_rdy = sec_rdy || mshr.io.req_sec_rdy
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fence = fence || !mshr.io.req_pri_rdy
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idx_match = idx_match || mshr.io.idx_match
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probe_idx_match = probe_idx_match || mshr.io.probe_idx_match
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refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready
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writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready
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mem_probe_rdy = mem_probe_rdy || mshr.io.mem_probe_ready
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}
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alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
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@ -443,14 +396,12 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
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mem_req_arb.io.out <> io.mem_req
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mem_finish_arb.io.out <> io.mem_finish
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wb_req_arb.io.out <> io.wb_req
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self_probe_arb.io.out <> io.self_probe
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.secondary_miss := idx_match
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io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id)
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io.fence_rdy := !fence
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io.mem_probe.ready := mem_probe_rdy
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//io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd)
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io.replay.bits.data := sdq(RegEn(replay_arb.io.out.bits.sdq_id, free_sdq))
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@ -573,7 +524,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
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state := s_release
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line_state := io.line_state
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way_en := io.way_en
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//when (!io.mshr_req.ready) { state := s_meta_read }
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when (!io.mshr_req.ready) { state := s_meta_read }
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}
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when (state === s_meta_resp) {
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state := s_mshr_req
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@ -599,7 +550,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
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io.meta_write.bits.data.state := conf.co.newStateOnProbe(req, line_state)
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io.meta_write.bits.data.tag := req.addr >> UFix(conf.idxbits)
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//io.mshr_req.valid := state === s_mshr_req
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io.mshr_req.valid := state === s_mshr_req
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io.wb_req.valid := state === s_writeback_req
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io.wb_req.bits.way_en := way_en
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io.wb_req.bits.idx := req.addr
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@ -962,10 +913,6 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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mshr.io.mem_rep.valid := io.mem.grant.fire()
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mshr.io.mem_rep.bits := io.mem.grant.bits.payload
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mshr.io.mem_abort.valid := io.mem.abort.valid
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mshr.io.mem_abort.bits := io.mem.abort.bits.payload
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io.mem.abort.ready := Bool(true)
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mshr.io.mem_probe <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
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when (mshr.io.req.fire()) { replacer.miss }
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io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready
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@ -990,9 +937,9 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
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val releaseArb = (new Arbiter(2)) { new Release }
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FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
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prober.io.req <> mshr.io.self_probe
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prober.io.req <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
|
||||
prober.io.rep <> releaseArb.io.in(1)
|
||||
//prober.io.mshr_req <> mshr.io.probe
|
||||
prober.io.mshr_req <> mshr.io.probe
|
||||
prober.io.wb_req <> wb.io.probe
|
||||
prober.io.way_en := s2_tag_match_way
|
||||
prober.io.line_state := s2_hit_state
|
||||
|
|
|
|||
|
|
@ -44,7 +44,6 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
|
|||
|
||||
io.tilelink.acquire <> arbiter.io.mem.acquire
|
||||
io.tilelink.acquire_data <> dcache.io.mem.acquire_data
|
||||
arbiter.io.mem.abort <> io.tilelink.abort
|
||||
arbiter.io.mem.grant <> io.tilelink.grant
|
||||
io.tilelink.grant_ack <> arbiter.io.mem.grant_ack
|
||||
dcache.io.mem.probe <> io.tilelink.probe
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user