riscv/rocket-chip
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remove aborts; simplify probes

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This commit is contained in:
Andrew Waterman
2013-03-19 15:29:40 -07:00
parent e0361840bd
commit ea9d0b771e
5 changed files with 14 additions and 91 deletions
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11
rocket/src/main/scala/arbiter.scala
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@ -50,7 +50,6 @@ class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Comp
class UncachedRequestorIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }}
val abort = (new MasterSourcedIO) {(new LogicalNetworkIO){new Abort }}
val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }}
val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }}
}
@ -101,14 +100,4 @@ class MemArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Com
io.requestor(i).grant.bits := io.mem.grant.bits
io.requestor(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
}
for (i <- 0 until n)
{
val tag = io.mem.abort.bits.payload.client_xact_id
io.requestor(i).abort.valid := io.mem.abort.valid && tag(log2Up(n)-1,0) === UFix(i)
io.requestor(i).abort.bits := io.mem.abort.bits
io.requestor(i).abort.bits.payload.client_xact_id := tag >> UFix(log2Up(n))
}
io.mem.abort.ready := Bool(true)
}

11
rocket/src/main/scala/htif.scala
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@ -105,15 +105,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
val mem_acked = Reg(resetVal = Bool(false))
val mem_gxid = Reg() { Bits() }
val mem_needs_ack = Reg() { Bool() }
val mem_nacked = Reg(resetVal = Bool(false))
when (io.mem.grant.valid) {
mem_acked := Bool(true)
mem_gxid := io.mem.grant.bits.payload.master_xact_id
mem_needs_ack := conf.co.requiresAck(io.mem.grant.bits.payload)
}
io.mem.grant.ready := Bool(true)
when (io.mem.abort.valid) { mem_nacked := Bool(true) }
io.mem.abort.ready := Bool(true)
val state_rx :: state_pcr_req :: state_pcr_resp :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(9) { UFix() }
val state = Reg(resetVal = state_rx)
@ -137,20 +134,12 @@ class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Compo
mem_cnt := mem_cnt + UFix(1)
}
when (state === state_mem_wresp) {
when (mem_nacked) {
state := state_mem_req
mem_nacked := Bool(false)
}
when (mem_acked) {
state := state_mem_finish
mem_acked := Bool(false)
}
}
when (state === state_mem_rdata) {
when (mem_nacked) {
state := state_mem_req
mem_nacked := Bool(false)
}
when (io.mem.grant.valid) {
when (mem_cnt.andR) {
state := state_mem_finish

1
rocket/src/main/scala/icache.scala
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@ -259,7 +259,6 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
when (io.mem.acquire.ready && finish_q.io.enq.ready) { state := s_refill_wait }
}
is (s_refill_wait) {
when (io.mem.abort.valid) { state := s_request }
when (io.mem.grant.valid) { state := s_refill }
}
is (s_refill) {

81
rocket/src/main/scala/nbdcache.scala
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@ -178,11 +178,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
val meta_read = (new FIFOIO) { new MetaReadReq }
val meta_write = (new FIFOIO) { new MetaWriteReq }
val replay = (new FIFOIO) { new Replay() }
val mem_abort = (new PipeIO) { new Abort }.flip
val mem_rep = (new PipeIO) { new Grant }.flip
val mem_probe = (new PipeIO) { new Probe }.flip
val mem_probe_ready = Bool(OUTPUT)
val self_probe = (new FIFOIO) { new InternalProbe }
val mem_finish = (new FIFOIO) { new GrantAck }
val wb_req = (new FIFOIO) { new WritebackReq }
val probe_writeback = (new FIFOIO) { Bool() }.flip
@ -197,32 +193,16 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
val line_state = Reg { UFix() }
val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) }
val req = Reg { new MSHRReq() }
val sent_wb_req = Reg { Bool() }
val req_cmd = io.req_bits.cmd
val req_idx = req.addr(conf.untagbits-1,conf.offbits)
val idx_match = req_idx === io.req_bits.addr(conf.untagbits-1,conf.offbits)
val probe_idx_match = req_idx === io.mem_probe.bits.addr(conf.untagbits-1,conf.offbits)
val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val abort = io.mem_abort.valid && io.mem_abort.bits.client_xact_id === UFix(id)
val reply = io.mem_rep.valid && io.mem_rep.bits.client_xact_id === UFix(id)
val refill_done = reply && refill_count.andR
val wb_done = reply && (state === s_wb_resp)
val probe_wb_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.old_meta.tag
val probe_tag_match = io.mem_probe.bits.addr >> conf.untagbits === req.addr >> conf.untagbits
val handle_probe = (state != s_invalid) && probe_idx_match
val kill_probe = sent_wb_req && probe_wb_tag_match && conf.co.pendingVoluntaryReleaseIsSufficient(release_type, io.mem_probe.bits.p_type)
val probe_q = (new Queue(1, pipe = true, flow = true)) { new Probe }
probe_q.io.enq.valid := io.mem_probe.valid && handle_probe && sent_wb_req && !kill_probe
io.mem_probe_ready := probe_q.io.enq.ready && handle_probe
probe_q.io.enq.bits := io.mem_probe.bits
io.self_probe.valid := probe_q.io.deq.valid && (state != s_wb_resp)
probe_q.io.deq.ready := io.self_probe.ready && (state != s_wb_resp)
io.self_probe.bits := probe_q.io.deq.bits
io.self_probe.bits.client_xact_id := UFix(id)
val rpq = (new Queue(conf.nrpq)) { new Replay }
rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd)
rpq.io.enq.bits := io.req_bits
@ -232,7 +212,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
val finish_q = (new Queue(2 /* wb + refill */)) { new GrantAck }
finish_q.io.enq.valid := (wb_done || refill_done) && conf.co.requiresAck(io.mem_rep.bits)
finish_q.io.enq.bits.master_xact_id := io.mem_rep.bits.master_xact_id
io.wb_req.valid := Bool(false)
when (state === s_drain_rpq && !rpq.io.deq.valid && !finish_q.io.deq.valid) {
state := s_invalid
@ -250,28 +229,18 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
refill_count := refill_count + UFix(1)
line_state := conf.co.newStateOnGrant(io.mem_rep.bits, io.mem_req.bits)
}
when (abort) { state := s_refill_req }
}
when (state === s_refill_req) {
when (abort) { state := s_refill_req }
.elsewhen (io.mem_req.ready) { state := s_refill_resp }
when (io.mem_req.ready) { state := s_refill_resp }
}
when (state === s_meta_clear && io.meta_write.ready) {
state := s_refill_req
}
when (state === s_wb_resp) {
when (reply) { state := s_meta_clear }
when (abort) { state := s_wb_req }
}
when (state === s_wb_req) {
io.wb_req.valid := Bool(true)
when (io.probe_writeback.valid && idx_match) {
io.wb_req.valid := Bool(false)
when (io.probe_writeback.bits) { state := s_refill_req }
}.elsewhen (io.wb_req.ready) {
sent_wb_req := Bool(true)
state := s_wb_resp
}
when (state === s_wb_req && io.wb_req.ready) {
state := s_wb_resp
}
when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
@ -283,7 +252,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
acquire_type := conf.co.getAcquireTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
release_type := conf.co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
req := io.req_bits
sent_wb_req := Bool(false)
state := Mux(conf.co.needsWriteback(io.req_bits.old_meta.state), s_wb_req, s_refill_req)
when (io.req_bits.tag_match) {
@ -297,7 +265,6 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
}
io.idx_match := (state != s_invalid) && idx_match
io.probe_idx_match := (state != s_invalid) && probe_idx_match
io.mem_resp := req
io.mem_resp.addr := Cat(req_idx, refill_count) << conf.ramoffbits
io.tag := req.addr >> conf.untagbits
@ -310,14 +277,15 @@ class MSHR(id: Int)(implicit conf: DCacheConfig) extends Component {
io.meta_write.bits.data.tag := io.tag
io.meta_write.bits.way_en := req.way_en
io.wb_req.valid := state === s_wb_req
io.wb_req.bits.tag := req.old_meta.tag
io.wb_req.bits.idx := req_idx
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.client_xact_id := Bits(id)
io.wb_req.bits.r_type := conf.co.getReleaseTypeOnVoluntaryWriteback()
io.probe_writeback.ready := (state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match
io.probe_refill.ready := (state != s_refill_resp && state != s_drain_rpq) || !idx_match
io.probe_writeback.ready := (state != s_wb_req && state != s_wb_resp && state != s_meta_clear && state != s_drain_rpq) || !idx_match
io.probe_refill.ready := (state != s_refill_resp && state != s_meta_write_req && state != s_meta_write_resp && state != s_drain_rpq) || !idx_match
io.mem_req.valid := state === s_refill_req
io.mem_req.bits.a_type := acquire_type
@ -349,12 +317,10 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
val meta_read = (new FIFOIO) { new MetaReadReq }
val meta_write = (new FIFOIO) { new MetaWriteReq }
val replay = (new FIFOIO) { new Replay }
val mem_abort = (new PipeIO) { new Abort }.flip
val mem_rep = (new PipeIO) { new Grant }.flip
val mem_finish = (new FIFOIO) { new GrantAck }
val wb_req = (new FIFOIO) { new WritebackReq }
val mem_probe = (new FIFOIO) { new Probe }.flip
val self_probe = (new FIFOIO) { new InternalProbe }
val probe = (new FIFOIO) { new Bool() }.flip
val fence_rdy = Bool(OUTPUT)
}
@ -375,7 +341,6 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
val mem_req_arb = (new Arbiter(conf.nmshr)) { new Acquire }
val mem_finish_arb = (new Arbiter(conf.nmshr)) { new GrantAck }
val wb_req_arb = (new Arbiter(conf.nmshr)) { new WritebackReq }
val self_probe_arb = (new Arbiter(conf.nmshr+1)) { new InternalProbe }
val replay_arb = (new Arbiter(conf.nmshr)) { new Replay() }
val alloc_arb = (new Arbiter(conf.nmshr)) { Bool() }
@ -383,18 +348,11 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.addr >> conf.untagbits
var idx_match = Bool(false)
var probe_idx_match = Bool(false)
var pri_rdy = Bool(false)
var fence = Bool(false)
var sec_rdy = Bool(false)
var writeback_probe_rdy = Bool(true)
var refill_probe_rdy = Bool(true)
var mem_probe_rdy = Bool(false)
self_probe_arb.io.in(0).valid := io.mem_probe.valid && !probe_idx_match
self_probe_arb.io.in(0).bits := io.mem_probe.bits
self_probe_arb.io.in(0).bits.client_xact_id := UFix(0) // DNC
mem_probe_rdy = mem_probe_rdy || self_probe_arb.io.in(0).ready
for (i <- 0 to conf.nmshr-1) {
val mshr = new MSHR(i)
@ -410,19 +368,16 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
mshr.io.req_bits := io.req.bits
mshr.io.req_sdq_id := sdq_alloc_id
mshr.io.mem_probe <> io.mem_probe
mshr.io.meta_read <> meta_read_arb.io.in(i)
mshr.io.meta_write <> meta_write_arb.io.in(i)
mshr.io.mem_req <> mem_req_arb.io.in(i)
mshr.io.mem_finish <> mem_finish_arb.io.in(i)
mshr.io.wb_req <> wb_req_arb.io.in(i)
mshr.io.self_probe <> self_probe_arb.io.in(i+1)
mshr.io.replay <> replay_arb.io.in(i)
mshr.io.probe_refill.valid := io.mem_probe.valid && tag_match
mshr.io.probe_writeback.valid := io.mem_probe.valid
mshr.io.probe_refill.valid := io.probe.valid && tag_match
mshr.io.probe_writeback.valid := io.probe.valid
mshr.io.probe_writeback.bits := wb_probe_match
mshr.io.mem_abort <> io.mem_abort
mshr.io.mem_rep <> io.mem_rep
memRespMux(i) := mshr.io.mem_resp
@ -430,10 +385,8 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
sec_rdy = sec_rdy || mshr.io.req_sec_rdy
fence = fence || !mshr.io.req_pri_rdy
idx_match = idx_match || mshr.io.idx_match
probe_idx_match = probe_idx_match || mshr.io.probe_idx_match
refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready
writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready
mem_probe_rdy = mem_probe_rdy || mshr.io.mem_probe_ready
}
alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
@ -443,14 +396,12 @@ class MSHRFile(implicit conf: DCacheConfig) extends Component {
mem_req_arb.io.out <> io.mem_req
mem_finish_arb.io.out <> io.mem_finish
wb_req_arb.io.out <> io.wb_req
self_probe_arb.io.out <> io.self_probe
io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
io.secondary_miss := idx_match
io.mem_resp := memRespMux(io.mem_rep.bits.client_xact_id)
io.fence_rdy := !fence
io.mem_probe.ready := mem_probe_rdy
//io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
val free_sdq = io.replay.fire() && isWrite(io.replay.bits.cmd)
io.replay.bits.data := sdq(RegEn(replay_arb.io.out.bits.sdq_id, free_sdq))
@ -573,7 +524,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
state := s_release
line_state := io.line_state
way_en := io.way_en
//when (!io.mshr_req.ready) { state := s_meta_read }
when (!io.mshr_req.ready) { state := s_meta_read }
}
when (state === s_meta_resp) {
state := s_mshr_req
@ -599,7 +550,7 @@ class ProbeUnit(implicit conf: DCacheConfig) extends Component {
io.meta_write.bits.data.state := conf.co.newStateOnProbe(req, line_state)
io.meta_write.bits.data.tag := req.addr >> UFix(conf.idxbits)
//io.mshr_req.valid := state === s_mshr_req
io.mshr_req.valid := state === s_mshr_req
io.wb_req.valid := state === s_writeback_req
io.wb_req.bits.way_en := way_en
io.wb_req.bits.idx := req.addr
@ -962,10 +913,6 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
mshr.io.mem_rep.valid := io.mem.grant.fire()
mshr.io.mem_rep.bits := io.mem.grant.bits.payload
mshr.io.mem_abort.valid := io.mem.abort.valid
mshr.io.mem_abort.bits := io.mem.abort.bits.payload
io.mem.abort.ready := Bool(true)
mshr.io.mem_probe <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
when (mshr.io.req.fire()) { replacer.miss }
io.mem.acquire.valid := mshr.io.mem_req.valid && prober.io.req.ready
@ -990,9 +937,9 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
val releaseArb = (new Arbiter(2)) { new Release }
FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
prober.io.req <> mshr.io.self_probe
prober.io.req <> FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
prober.io.rep <> releaseArb.io.in(1)
//prober.io.mshr_req <> mshr.io.probe
prober.io.mshr_req <> mshr.io.probe
prober.io.wb_req <> wb.io.probe
prober.io.way_en := s2_tag_match_way
prober.io.line_state := s2_hit_state

1
rocket/src/main/scala/tile.scala
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@ -44,7 +44,6 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
io.tilelink.acquire <> arbiter.io.mem.acquire
io.tilelink.acquire_data <> dcache.io.mem.acquire_data
arbiter.io.mem.abort <> io.tilelink.abort
arbiter.io.mem.grant <> io.tilelink.grant
io.tilelink.grant_ack <> arbiter.io.mem.grant_ack
dcache.io.mem.probe <> io.tilelink.probe