support memory transaction aborts
This commit is contained in:
parent
950b5cd900
commit
5f12990dfb
@ -4,62 +4,74 @@ import Chisel._;
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import Node._;
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import Constants._;
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class ioUncachedRequestor extends Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }.flip
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val xact_rep = (new ioPipe) { new TransactionReply() }.flip
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }
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}
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class rocketMemArbiter(n: Int) extends Component {
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val io = new Bundle {
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val mem = new ioTileLink
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val requestor = Vec(n) { new ioTileLink().flip }
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val mem = new ioUncachedRequestor
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val requestor = Vec(n) { new ioUncachedRequestor().flip }
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}
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var req_val = Bool(false)
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var req_rdy = io.mem.xact_init.ready
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var xi_val = Bool(false)
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var xi_rdy = io.mem.xact_init.ready
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for (i <- 0 until n)
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{
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io.requestor(i).xact_init.ready := req_rdy
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req_val = req_val || io.requestor(i).xact_init.valid
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req_rdy = req_rdy && !io.requestor(i).xact_init.valid
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io.requestor(i).xact_init.ready := xi_rdy
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xi_val = xi_val || io.requestor(i).xact_init.valid
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xi_rdy = xi_rdy && !io.requestor(i).xact_init.valid
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}
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// if more than one requestor at a time can write back, the data
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// arbiter needs to be made stateful: one xact's write data must
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// be sent to the memory system contiguously.
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var req_data_val = Bool(false)
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var req_data_rdy = io.mem.xact_init_data.ready
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var xi_bits = Wire() { new TransactionInit }
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xi_bits := io.requestor(n-1).xact_init.bits
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xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2up(n)))
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for (i <- n-2 to 0 by -1)
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{
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var my_xi_bits = Wire() { new TransactionInit }
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my_xi_bits := io.requestor(i).xact_init.bits
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my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2up(n)))
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xi_bits = Mux(io.requestor(i).xact_init.valid, my_xi_bits, xi_bits)
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}
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io.mem.xact_init.valid := xi_val
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io.mem.xact_init.bits := xi_bits
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var xf_val = Bool(false)
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var xf_rdy = io.mem.xact_finish.ready
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for (i <- 0 until n)
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{
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io.requestor(i).xact_init_data.ready := req_data_rdy
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req_data_val = req_data_val || io.requestor(i).xact_init_data.valid
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req_data_rdy = req_data_rdy && !io.requestor(i).xact_init_data.valid
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io.requestor(i).xact_finish.ready := xf_rdy
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xf_val = xf_val || io.requestor(i).xact_finish.valid
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xf_rdy = xf_rdy && !io.requestor(i).xact_finish.valid
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}
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var req_bits = Wire() { new TransactionInit }
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req_bits := io.requestor(n-1).xact_init.bits
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req_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2up(n)))
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var xf_bits = io.requestor(n-1).xact_finish.bits
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for (i <- n-2 to 0 by -1)
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{
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var my_req_bits = Wire() { new TransactionInit }
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my_req_bits := io.requestor(i).xact_init.bits
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my_req_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2up(n)))
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xf_bits = Mux(io.requestor(i).xact_finish.valid, io.requestor(i).xact_finish.bits, xf_bits)
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req_bits = Mux(io.requestor(i).xact_init.valid, my_req_bits, req_bits)
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}
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var req_data_bits = io.requestor(n-1).xact_init_data.bits
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for (i <- n-2 to 0 by -1)
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req_data_bits = Mux(io.requestor(i).xact_init_data.valid, io.requestor(i).xact_init_data.bits, req_data_bits)
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io.mem.xact_init.valid := req_val
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io.mem.xact_init.bits := req_bits
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io.mem.xact_init_data.valid := req_data_val
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io.mem.xact_init_data.bits := req_data_bits
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io.mem.xact_finish.valid := xf_val
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io.mem.xact_finish.bits := xf_bits
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for (i <- 0 until n)
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{
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val tag = io.mem.xact_rep.bits.tile_xact_id
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io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2up(n)-1,0) === UFix(i)
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io.requestor(i).xact_rep.bits.data := io.mem.xact_rep.bits.data
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io.requestor(i).xact_rep.bits.t_type := io.mem.xact_rep.bits.t_type
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io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits
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io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2up(n))
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io.requestor(i).xact_rep.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
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}
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for (i <- 0 until n)
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{
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val tag = io.mem.xact_abort.bits.tile_xact_id
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io.requestor(i).xact_abort.valid := io.mem.xact_abort.valid && tag(log2up(n)-1,0) === UFix(i)
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io.requestor(i).xact_abort.bits := io.mem.xact_abort.bits
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io.requestor(i).xact_abort.bits.tile_xact_id := tag >> UFix(log2up(n))
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}
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io.mem.xact_abort.ready := Bool(true)
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}
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@ -395,6 +395,8 @@ class CoherenceHubNull extends CoherenceHub {
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.bits.data := io.mem.resp.bits.data
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x_rep.valid := io.mem.resp.valid || x_init.valid && is_write
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io.tiles(0).xact_abort.valid := Bool(false)
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}
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@ -186,7 +186,7 @@ object Constants
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val NTILES = 1
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val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
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val TILE_ID_BITS = 1
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val TILE_XACT_ID_BITS = log2up(NMSHR)+2
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val TILE_XACT_ID_BITS = log2up(NMSHR)+3
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val GLOBAL_XACT_ID_BITS = 4
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val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
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@ -78,7 +78,12 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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Mux(!nack && cmd === cmd_readcr, UFix(1), UFix(0)))
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val tx_done = packet_ram_raddr - UFix(1) === tx_size
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val state_rx :: state_pcr :: state_mem_req :: state_mem_wdata :: state_mem_rdata :: state_tx :: Nil = Enum(6) { UFix() }
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val mem_acked = Reg(resetVal = Bool(false))
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val mem_nacked = Reg(resetVal = Bool(false))
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when (io.mem.xact_rep.valid) { mem_acked := Bool(true) }
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when (io.mem.xact_abort.valid) { mem_nacked := Bool(true) }
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val state_rx :: state_pcr :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_tx :: Nil = Enum(7) { UFix() }
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val state = Reg(resetVal = state_rx)
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when (state === state_rx && rx_done) {
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@ -96,13 +101,35 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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when (state === state_mem_req && io.mem.xact_init.ready) {
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state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata)
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}
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when (state === state_mem_wdata && io.mem.xact_init_data.ready ||
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state === state_mem_rdata && io.mem.xact_rep.valid) {
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when (state === state_mem_wdata && io.mem.xact_init_data.ready) {
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when (mem_cnt.andR) {
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state := state_tx
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state := state_mem_wresp
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}
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mem_cnt := mem_cnt + UFix(1)
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}
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when (state === state_mem_wresp) {
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when (mem_nacked) {
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state := state_mem_req
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mem_nacked := Bool(false)
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}
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when (mem_acked) {
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state := state_tx
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mem_acked := Bool(false)
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}
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}
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when (state === state_mem_rdata) {
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when (mem_nacked) {
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state := state_mem_req
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mem_nacked := Bool(false)
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}
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when (io.mem.xact_rep.valid) {
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when (mem_cnt.andR) {
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state := state_tx
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}
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mem_cnt := mem_cnt + UFix(1)
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}
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mem_acked := Bool(false)
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}
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when (state === state_tx && tx_done) {
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rx_count := UFix(0)
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tx_count := UFix(0)
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@ -20,7 +20,7 @@ class ioImem(view: List[String] = null) extends Bundle (view)
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class ioRocketICache extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioTileLink
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val mem = new ioUncachedRequestor
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}
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// basic direct mapped instruction cache
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@ -49,6 +49,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
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val state = Reg(resetVal = s_reset);
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val invalidated = Reg() { Bool() }
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val r_cpu_req_idx = Reg { Bits() }
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val r_cpu_req_ppn = Reg { Bits() }
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@ -78,13 +79,14 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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when (io.mem.xact_rep.valid) {
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refill_count := refill_count + UFix(1);
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}
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val refill_done = io.mem.xact_rep.valid && refill_count.andR
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val repl_way = LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0)
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val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
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val tag_we = (state === s_refill) && refill_done
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val tag_addr =
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Mux((state === s_refill_wait), r_cpu_req_idx(indexmsb,indexlsb),
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Mux((state === s_refill), r_cpu_req_idx(indexmsb,indexlsb),
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io.cpu.req_idx(indexmsb,indexlsb)).toUFix;
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val tag_we = (state === s_refill_wait) && io.mem.xact_rep.valid;
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val data_addr =
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count),
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io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix;
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@ -102,10 +104,10 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, sets));
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when (io.cpu.invalidate) {
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vb_array := Bits(0,sets);
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vb_array := Bits(0)
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}
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.elsewhen (tag_we && repl_me) {
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vb_array := vb_array.bitSet(r_cpu_req_idx(indexmsb,indexlsb).toUFix, UFix(1,1));
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vb_array := vb_array.bitSet(r_cpu_req_idx(indexmsb,indexlsb).toUFix, !invalidated)
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}
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val valid = vb_array(r_cpu_req_idx(indexmsb,indexlsb)).toBool;
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@ -131,20 +133,20 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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io.mem.xact_init.valid := (state === s_request)
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io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
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io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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io.mem.xact_init_data.valid := Bool(false)
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// control state machine
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when (io.cpu.invalidate) {
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invalidated := Bool(true)
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}
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switch (state) {
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is (s_reset) {
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state := s_ready;
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}
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is (s_ready) {
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when (io.cpu.itlb_miss) {
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state := s_ready;
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}
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.elsewhen (r_cpu_req_val && !tag_hit) {
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when (r_cpu_req_val && !tag_hit && !io.cpu.itlb_miss) {
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state := s_request;
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}
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invalidated := Bool(false)
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}
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is (s_request)
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{
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@ -153,12 +155,15 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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}
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}
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is (s_refill_wait) {
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when (io.mem.xact_abort.valid) {
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state := s_request
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}
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when (io.mem.xact_rep.valid) {
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state := s_refill;
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}
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}
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is (s_refill) {
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when (io.mem.xact_rep.valid && refill_count.andR) {
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when (refill_done) {
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state := s_ready;
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}
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}
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@ -18,22 +18,23 @@ class rocketIPrefetcher extends Component() {
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val s_invalid :: s_valid :: s_refilling :: s_req_wait :: s_resp_wait :: s_bad_resp_wait :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_invalid);
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val ip_mem_resp_abort = io.mem.xact_abort.valid && io.mem.xact_abort.bits.tile_xact_id(0)
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val demand_miss = io.icache.xact_init.valid && io.icache.xact_init.ready
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val prefetch_addr = Reg() { UFix(width = io.icache.xact_init.bits.address.width) };
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val addr_match = (prefetch_addr === io.icache.xact_init.bits.address);
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val hit = (state != s_invalid) & (state != s_req_wait) & addr_match;
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val hit = (state != s_invalid) && (state != s_req_wait) && addr_match && !ip_mem_resp_abort
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val prefetch_miss = io.icache.xact_init.valid && !hit
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when (demand_miss) { prefetch_addr := io.icache.xact_init.bits.address + UFix(1); }
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io.icache.xact_init.ready := io.mem.xact_init.ready
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val ip_mem_req_rdy = io.mem.xact_init.ready && !prefetch_miss
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val ip_mem_resp_val = io.mem.xact_rep.valid && io.mem.xact_rep.bits.tile_xact_id(0)
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val ip_mem_req_rdy = io.mem.xact_init.ready && !prefetch_miss
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io.mem.xact_abort.ready := Bool(true)
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io.mem.xact_init.valid := prefetch_miss || (state === s_req_wait)
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io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
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io.mem.xact_init.bits.tile_xact_id := Mux(prefetch_miss, UFix(0), UFix(1))
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io.mem.xact_init.bits.address := Mux(prefetch_miss, io.icache.xact_init.bits.address, prefetch_addr);
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io.mem.xact_init_data.valid := Bool(false)
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val fill_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (ip_mem_resp_val.toBool) { fill_cnt := fill_cnt + UFix(1); }
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@ -43,8 +44,10 @@ class rocketIPrefetcher extends Component() {
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val forward_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (forward & pdq.io.deq.valid) { forward_cnt := forward_cnt + UFix(1); }
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val forward_done = (~forward_cnt === UFix(0)) & pdq.io.deq.valid;
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forward := (demand_miss & hit | forward & ~forward_done);
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forward := demand_miss && hit || forward && !forward_done
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io.icache.xact_abort.valid := io.mem.xact_abort.valid && !io.mem.xact_abort.bits.tile_xact_id(0) ||
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forward && ip_mem_resp_abort
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io.icache.xact_rep.valid := io.mem.xact_rep.valid && !io.mem.xact_rep.bits.tile_xact_id(0) || (forward && pdq.io.deq.valid)
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io.icache.xact_rep.bits.data := Mux(forward, pdq.io.deq.bits, io.mem.xact_rep.bits.data)
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@ -69,11 +72,14 @@ class rocketIPrefetcher extends Component() {
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when (ip_mem_req_rdy) { state := s_resp_wait; }
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}
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is (s_resp_wait) {
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when (demand_miss & ~addr_match) { state := s_bad_resp_wait; }
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.elsewhen (ip_mem_resp_val.toBool) { state := s_refilling; }
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when (ip_mem_resp_abort) {
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state := s_invalid
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}
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.elsewhen (demand_miss && !addr_match) { state := s_bad_resp_wait }
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.elsewhen (ip_mem_resp_val) { state := s_refilling }
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}
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is (s_bad_resp_wait) {
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when (fill_done.toBool & ip_mem_resp_val.toBool) { state := s_req_wait; }
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when (fill_done || ip_mem_resp_abort) { state := s_req_wait }
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}
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}
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@ -178,6 +178,7 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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val way_oh = Bits(NWAYS, OUTPUT)
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val mem_resp_val = Bool(INPUT)
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val mem_abort_val = Bool(INPUT)
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val mem_req = (new ioDecoupled) { new TransactionInit }
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
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val replay = (new ioDecoupled) { new Replay() }
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@ -216,6 +217,9 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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when (io.mem_req.valid && io.mem_req.ready) {
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requested := Bool(true)
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}
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when (io.mem_abort_val) {
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requested := Bool(false)
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}
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when (io.mem_resp_val) {
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refilled := Bool(true)
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}
|
||||
@ -264,6 +268,7 @@ class MSHRFile extends Component {
|
||||
val mem_req = (new ioDecoupled) { new TransactionInit }
|
||||
val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
|
||||
val data_req = (new ioDecoupled) { new DataReq() }
|
||||
val mem_abort = (new ioPipe) { new TransactionAbort }.flip
|
||||
|
||||
val cpu_resp_val = Bool(OUTPUT)
|
||||
val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
|
||||
@ -310,8 +315,8 @@ class MSHRFile extends Component {
|
||||
mshr.io.mem_req <> mem_req_arb.io.in(i)
|
||||
mshr.io.replay <> replay_arb.io.in(i)
|
||||
|
||||
val mem_resp_val = io.mem_resp_val && (UFix(i) === io.mem_resp_tag)
|
||||
mshr.io.mem_resp_val := mem_resp_val
|
||||
mshr.io.mem_resp_val := io.mem_resp_val && (UFix(i) === io.mem_resp_tag)
|
||||
mshr.io.mem_abort_val := io.mem_abort.valid && (UFix(i) === io.mem_abort.bits.tile_xact_id)
|
||||
mem_resp_idx_mux.io.sel(i) := (UFix(i) === io.mem_resp_tag)
|
||||
mem_resp_idx_mux.io.in(i) := mshr.io.idx
|
||||
mem_resp_way_oh_mux.io.sel(i) := (UFix(i) === io.mem_resp_tag)
|
||||
@ -352,22 +357,55 @@ class WritebackUnit extends Component {
|
||||
val data_req = (new ioDecoupled) { new DataArrayArrayReq() }
|
||||
val data_resp = Bits(MEM_DATA_BITS, INPUT)
|
||||
val refill_req = (new ioDecoupled) { new TransactionInit }.flip
|
||||
val mem_req = (new ioDecoupled) { new TransactionInit }
|
||||
val mem_req = (new ioDecoupled) { new TransactionInit }
|
||||
val mem_req_data = (new ioDecoupled) { new TransactionInitData }
|
||||
val mem_abort = (new ioPipe) { new TransactionAbort }.flip
|
||||
val mem_rep = (new ioPipe) { new TransactionReply }.flip
|
||||
}
|
||||
|
||||
val valid = Reg(resetVal = Bool(false))
|
||||
val data_req_fired = Reg(resetVal = Bool(false))
|
||||
val cmd_sent = Reg() { Bool() }
|
||||
val cnt = Reg() { UFix(width = log2up(REFILL_CYCLES+1)) }
|
||||
val addr = Reg() { new WritebackReq() }
|
||||
|
||||
data_req_fired := Bool(false)
|
||||
when (io.data_req.valid && io.data_req.ready) { data_req_fired := Bool(true); cnt := cnt + UFix(1) }
|
||||
when (data_req_fired && !io.mem_req_data.ready) { data_req_fired := Bool(false); cnt := cnt - UFix(1) }
|
||||
when ((cnt === UFix(REFILL_CYCLES)) && io.mem_req_data.ready) { valid := Bool(false) }
|
||||
when (io.req.valid && io.req.ready) { valid := Bool(true); cnt := UFix(0); addr := io.req.bits }
|
||||
val acked = Reg() { Bool() }
|
||||
val nacked = Reg() { Bool() }
|
||||
when (io.mem_rep.valid && io.mem_rep.bits.tile_xact_id === UFix(NMSHR)) { acked := Bool(true) }
|
||||
when (io.mem_abort.valid && io.mem_abort.bits.tile_xact_id === UFix(NMSHR)) { nacked := Bool(true) }
|
||||
|
||||
io.req.ready := !valid && io.mem_req.ready
|
||||
data_req_fired := Bool(false)
|
||||
when (valid && io.mem_req.ready) {
|
||||
cmd_sent := Bool(true)
|
||||
}
|
||||
when (io.data_req.valid && io.data_req.ready) {
|
||||
data_req_fired := Bool(true)
|
||||
cnt := cnt + UFix(1)
|
||||
}
|
||||
when (data_req_fired && !io.mem_req_data.ready) {
|
||||
data_req_fired := Bool(false)
|
||||
cnt := cnt - UFix(1)
|
||||
}
|
||||
when ((cnt === UFix(REFILL_CYCLES)) && (!data_req_fired || io.mem_req_data.ready)) {
|
||||
when (acked) {
|
||||
valid := Bool(false)
|
||||
}
|
||||
when (nacked) {
|
||||
cmd_sent := Bool(false)
|
||||
nacked := Bool(false)
|
||||
cnt := UFix(0)
|
||||
}
|
||||
}
|
||||
when (io.req.valid && io.req.ready) {
|
||||
valid := Bool(true)
|
||||
acked := Bool(false)
|
||||
nacked := Bool(false)
|
||||
cmd_sent := Bool(false)
|
||||
cnt := UFix(0)
|
||||
addr := io.req.bits
|
||||
}
|
||||
|
||||
io.req.ready := !valid
|
||||
io.data_req.valid := valid && (cnt < UFix(REFILL_CYCLES))
|
||||
io.data_req.bits.way_en := addr.way_oh
|
||||
io.data_req.bits.inner_req.idx := addr.idx
|
||||
@ -376,11 +414,12 @@ class WritebackUnit extends Component {
|
||||
io.data_req.bits.inner_req.wmask := Bits(0)
|
||||
io.data_req.bits.inner_req.data := Bits(0)
|
||||
|
||||
val wb_req_val = io.req.valid && !valid
|
||||
io.refill_req.ready := io.mem_req.ready && !wb_req_val
|
||||
io.mem_req.valid := io.refill_req.valid || wb_req_val
|
||||
val wb_req_val = valid && !cmd_sent
|
||||
io.refill_req.ready := io.mem_req.ready && !(valid && !acked)
|
||||
io.mem_req.valid := io.refill_req.valid && !(valid && !acked) || wb_req_val
|
||||
io.mem_req.bits.t_type := Mux(wb_req_val, X_INIT_WRITE_UNCACHED, io.refill_req.bits.t_type)
|
||||
io.mem_req.bits.address := Mux(wb_req_val, Cat(io.req.bits.ppn, io.req.bits.idx).toUFix, io.refill_req.bits.address)
|
||||
io.mem_req.bits.has_data := wb_req_val
|
||||
io.mem_req.bits.address := Mux(wb_req_val, Cat(addr.ppn, addr.idx).toUFix, io.refill_req.bits.address)
|
||||
io.mem_req.bits.tile_xact_id := Mux(wb_req_val, Bits(NMSHR), io.refill_req.bits.tile_xact_id)
|
||||
|
||||
io.mem_req_data.valid := data_req_fired
|
||||
@ -676,8 +715,12 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
|
||||
val cpu_req_data = Mux(r_replay_amo, r_amo_replay_data, io.cpu.req_data)
|
||||
|
||||
// refill counter
|
||||
<<<<<<< HEAD
|
||||
val mem_resp_type = io.mem.xact_rep.bits.t_type
|
||||
val refill_val = io.mem.xact_rep.valid && (mem_resp_type === X_REP_READ_SHARED || mem_resp_type === X_REP_READ_EXCLUSIVE)
|
||||
=======
|
||||
val refill_val = io.mem.xact_rep.valid && io.mem.xact_rep.bits.tile_xact_id < UFix(NMSHR)
|
||||
>>>>>>> support memory transaction aborts
|
||||
val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
|
||||
val rr_count_next = rr_count + UFix(1)
|
||||
when (refill_val) { rr_count := rr_count_next }
|
||||
@ -725,6 +768,9 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
|
||||
wb_arb.io.out <> wb.io.req
|
||||
wb.io.data_req <> data_arb.io.in(3)
|
||||
wb.io.data_resp <> data_resp_mux
|
||||
wb.io.mem_rep <> io.mem.xact_rep
|
||||
wb.io.mem_abort.valid := io.mem.xact_abort.valid
|
||||
wb.io.mem_abort.bits := io.mem.xact_abort.bits
|
||||
|
||||
// replacement policy
|
||||
val replacer = new RandomReplacementWayGen()
|
||||
@ -737,9 +783,11 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
|
||||
// refill response
|
||||
val block_during_refill = !refill_val && (rr_count != UFix(0))
|
||||
data_arb.io.in(0).bits.inner_req.offset := rr_count
|
||||
data_arb.io.in(0).bits.inner_req.idx := mshr.io.mem_resp_idx
|
||||
data_arb.io.in(0).bits.inner_req.rw := !block_during_refill
|
||||
data_arb.io.in(0).bits.inner_req.wmask := ~UFix(0, MEM_DATA_BITS/8)
|
||||
data_arb.io.in(0).bits.inner_req.data := io.mem.xact_rep.bits.data
|
||||
data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
|
||||
data_arb.io.in(0).valid := refill_val || block_during_refill
|
||||
|
||||
// load hits
|
||||
@ -815,10 +863,10 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
|
||||
|
||||
mshr.io.mem_resp_val := refill_val && (~rr_count === UFix(0))
|
||||
mshr.io.mem_resp_tag := io.mem.xact_rep.bits.tile_xact_id
|
||||
mshr.io.mem_abort.valid := io.mem.xact_abort.valid
|
||||
mshr.io.mem_abort.bits := io.mem.xact_abort.bits
|
||||
mshr.io.mem_req <> wb.io.refill_req
|
||||
mshr.io.meta_req <> meta_arb.io.in(1)
|
||||
data_arb.io.in(0).bits.inner_req.idx := mshr.io.mem_resp_idx
|
||||
data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
|
||||
replacer.io.pick_new_way := mshr.io.req.valid && mshr.io.req.ready
|
||||
|
||||
// replays
|
||||
|
@ -29,13 +29,18 @@ class Top() extends Component {
|
||||
val hub = new CoherenceHubNull
|
||||
// connect tile to hub
|
||||
hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init)
|
||||
hub.io.tiles(0).xact_init_data <> Queue(arbiter.io.mem.xact_init_data)
|
||||
arbiter.io.mem.xact_abort <> Queue(hub.io.tiles(0).xact_abort)
|
||||
arbiter.io.mem.xact_rep <> Pipe(hub.io.tiles(0).xact_rep)
|
||||
// connect hub to memory
|
||||
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
|
||||
io.mem.req_data <> Queue(hub.io.mem.req_data)
|
||||
hub.io.mem.resp <> Pipe(io.mem.resp)
|
||||
|
||||
// temporary HTIF data connection
|
||||
val data_arb = (new Arbiter(2)) { new TransactionInitData }
|
||||
data_arb.io.in(0) <> Queue(dcache.io.mem.xact_init_data)
|
||||
data_arb.io.in(1) <> Queue(htif.io.mem.xact_init_data)
|
||||
hub.io.tiles(0).xact_init_data <> data_arb.io.out
|
||||
|
||||
if (HAVE_VEC)
|
||||
{
|
||||
|
Loading…
Reference in New Issue
Block a user