Removed has_data fields from all coherence messages, increased message type names to compensate
This commit is contained in:
parent
35f97bf858
commit
1b3307df32
@ -42,8 +42,7 @@ class TrackerAllocReq extends Bundle {
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class TransactionInit extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val t_type = Bits(width = X_INIT_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = UFix(width = PADDR_BITS)
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}
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@ -55,21 +54,20 @@ class TransactionAbort extends Bundle {
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}
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class ProbeRequest extends Bundle {
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val p_type = Bits(width = PTYPE_BITS)
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val p_type = Bits(width = P_REQ_TYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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class ProbeReply extends Bundle {
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val p_type = Bits(width = PTYPE_BITS)
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val has_data = Bool()
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val p_type = Bits(width = P_REP_TYPE_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends MemData
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class TransactionReply extends MemData {
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val t_type = Bits(width = TTYPE_BITS)
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val t_type = Bits(width = X_REP_TYPE_BITS)
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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@ -162,17 +160,17 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.t_type, tileInvalid, Array(
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X_READ_SHARED -> tileShared,
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X_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
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X_READ_EXCLUSIVE_ACK -> tileExclusiveDirty,
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X_READ_UNCACHED -> tileInvalid,
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X_WRITE_UNCACHED -> tileInvalid
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X_REP_READ_SHARED -> tileShared,
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X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
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X_REP_READ_EXCLUSIVE_ACK -> tileExclusiveDirty,
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X_REP_READ_UNCACHED -> tileInvalid,
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X_REP_WRITE_UNCACHED -> tileInvalid
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))
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}
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def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.t_type === X_READ_UNCACHED || outstanding.t_type === X_WRITE_UNCACHED)) ||
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(write && (outstanding.t_type != X_READ_EXCLUSIVE))
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(read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) ||
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(write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE))
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}
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def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = {
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@ -183,12 +181,20 @@ trait FourStateCoherence extends CoherencePolicy {
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))
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}
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def replyTypeHasData (reply: TransactionReply): Bool = {
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(reply.t_type != X_WRITE_UNCACHED && reply.t_type != X_READ_EXCLUSIVE_ACK)
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def probeReplyHasData (reply: ProbeReply): Bool = {
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(reply.p_type === P_REP_INVALIDATE_DATA ||
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reply.p_type === P_REP_DOWNGRADE_DATA ||
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reply.p_type === P_REP_COPY_DATA)
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}
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def transactionInitHasData (init: TransactionInit): Bool = {
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(init.t_type != X_INIT_WRITE_UNCACHED)
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}
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def transactionReplyHasData (reply: TransactionReply): Bool = {
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(reply.t_type != X_REP_WRITE_UNCACHED && reply.t_type != X_REP_READ_EXCLUSIVE_ACK)
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}
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}
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class XactTracker(id: Int) extends Component with CoherencePolicy {
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class XactTracker(id: Int) extends Component with FourStateCoherence {
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val io = new Bundle {
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq }.flip
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val p_data = (new ioPipe) { new TrackerProbeData }
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@ -210,7 +216,7 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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val t_type = Bits(X_INIT_TYPE_BITS, OUTPUT)
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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@ -220,18 +226,20 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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}
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def sendProbeReqType(t_type: UFix, global_state: UFix): UFix = {
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MuxCase(P_COPY, Array((t_type === X_READ_SHARED) -> P_DOWNGRADE,
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(t_type === X_READ_EXCLUSIVE) -> P_INVALIDATE,
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(t_type === X_READ_UNCACHED) -> P_COPY,
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(t_type === X_WRITE_UNCACHED) -> P_INVALIDATE))
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MuxLookup(t_type, P_REQ_COPY, Array(
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X_INIT_READ_SHARED -> P_REQ_DOWNGRADE,
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X_INIT_READ_EXCLUSIVE -> P_REQ_INVALIDATE,
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X_INIT_READ_UNCACHED -> P_REQ_COPY,
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X_INIT_WRITE_UNCACHED -> P_REQ_INVALIDATE
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))
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}
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def needsMemRead(t_type: UFix, global_state: UFix): Bool = {
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(t_type != X_WRITE_UNCACHED)
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(t_type != X_INIT_WRITE_UNCACHED)
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}
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def needsAckRep(t_type: UFix, global_state: UFix): Bool = {
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(t_type === X_WRITE_UNCACHED)
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(t_type === X_INIT_WRITE_UNCACHED)
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}
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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@ -312,7 +320,7 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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t_type_ := io.alloc_req.bits.xact_init.t_type
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init_tile_id_ := io.alloc_req.bits.init_tile_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := io.alloc_req.bits.xact_init.has_data
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x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init)
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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p_rep_count := UFix(NTILES-1)
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.init_tile_id )
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@ -378,7 +386,7 @@ abstract class CoherenceHub extends Component with CoherencePolicy {
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class CoherenceHubNull extends CoherenceHub {
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val x_init = io.tiles(0).xact_init
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val is_write = x_init.bits.t_type === X_WRITE_UNCACHED
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val is_write = x_init.bits.t_type === X_INIT_WRITE_UNCACHED
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x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
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io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
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io.mem.req_cmd.bits.rw := is_write
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@ -387,7 +395,7 @@ class CoherenceHubNull extends CoherenceHub {
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io.mem.req_data <> io.tiles(0).xact_init_data
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val x_rep = io.tiles(0).xact_rep
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x_rep.bits.t_type := Mux(io.mem.resp.valid, X_READ_EXCLUSIVE, X_WRITE_UNCACHED)
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x_rep.bits.t_type := Mux(io.mem.resp.valid, X_REP_READ_EXCLUSIVE, X_REP_WRITE_UNCACHED)
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x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.bits.data := io.mem.resp.bits.data
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@ -395,17 +403,17 @@ class CoherenceHubNull extends CoherenceHub {
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}
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class CoherenceHubBroadcast extends CoherenceHub {
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class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
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addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
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}
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def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
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MuxLookup(t_type, X_READ_UNCACHED, Array(
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X_READ_SHARED -> Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE),
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X_READ_EXCLUSIVE -> X_READ_EXCLUSIVE,
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X_READ_UNCACHED -> X_READ_UNCACHED,
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X_WRITE_UNCACHED -> X_WRITE_UNCACHED
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MuxLookup(t_type, X_REP_READ_UNCACHED, Array(
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X_INIT_READ_SHARED -> Mux(count > UFix(0), X_REP_READ_SHARED, X_REP_READ_EXCLUSIVE),
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X_INIT_READ_EXCLUSIVE -> X_REP_READ_EXCLUSIVE,
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X_INIT_READ_UNCACHED -> X_REP_READ_UNCACHED,
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X_INIT_WRITE_UNCACHED -> X_REP_WRITE_UNCACHED
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))
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}
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@ -415,7 +423,7 @@ class CoherenceHubBroadcast extends CoherenceHub {
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val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} }
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val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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@ -506,7 +514,7 @@ class CoherenceHubBroadcast extends CoherenceHub {
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val idx = p_rep.bits.global_xact_id
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p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _)
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p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
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p_data_valid_arr(idx) := p_rep.valid && p_rep.bits.has_data
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p_data_valid_arr(idx) := p_rep.valid && probeReplyHasData(p_rep.bits)
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p_data_tile_id_arr(idx) := UFix(j)
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}
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for( i <- 0 until NGLOBAL_XACTS ) {
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@ -527,7 +535,7 @@ class CoherenceHubBroadcast extends CoherenceHub {
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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conflicts(UFix(i), t.busy && coherenceConflict(t.addr, x_init.bits.address) &&
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!(x_init.bits.has_data && (UFix(j) === t.init_tile_id)))
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!(transactionInitHasData(x_init.bits) && (UFix(j) === t.init_tile_id)))
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// Don't abort writebacks stalled on mem.
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// TODO: This assumes overlapped writeback init reqs to
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// the same addr will never be issued; is this ok?
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@ -191,16 +191,31 @@ object Constants
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val GLOBAL_XACT_ID_BITS = 4
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val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
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val TTYPE_BITS = 2
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val X_READ_SHARED = UFix(0, TTYPE_BITS)
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val X_READ_EXCLUSIVE = UFix(1, TTYPE_BITS)
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val X_READ_UNCACHED = UFix(2, TTYPE_BITS)
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val X_WRITE_UNCACHED = UFix(3, TTYPE_BITS)
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val X_INIT_TYPE_BITS = 2
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val X_INIT_READ_SHARED = UFix(0, X_INIT_TYPE_BITS)
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val X_INIT_READ_EXCLUSIVE = UFix(1, X_INIT_TYPE_BITS)
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val X_INIT_READ_UNCACHED = UFix(2, X_INIT_TYPE_BITS)
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val X_INIT_WRITE_UNCACHED = UFix(3, X_INIT_TYPE_BITS)
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val PTYPE_BITS = 2
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val P_INVALIDATE = UFix(0, PTYPE_BITS)
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val P_DOWNGRADE = UFix(1, PTYPE_BITS)
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val P_COPY = UFix(2, PTYPE_BITS)
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val X_REP_TYPE_BITS = 3
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val X_REP_READ_SHARED = UFix(0, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE = UFix(1, X_REP_TYPE_BITS)
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val X_REP_READ_UNCACHED = UFix(2, X_REP_TYPE_BITS)
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val X_REP_WRITE_UNCACHED = UFix(3, X_REP_TYPE_BITS)
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val X_REP_READ_EXCLUSIVE_ACK = UFix(4, X_REP_TYPE_BITS)
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val P_REQ_TYPE_BITS = 2
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val P_REQ_INVALIDATE = UFix(0, P_REQ_TYPE_BITS)
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val P_REQ_DOWNGRADE = UFix(1, P_REQ_TYPE_BITS)
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val P_REQ_COPY = UFix(2, P_REQ_TYPE_BITS)
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val P_REP_TYPE_BITS = 3
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val P_REP_INVALIDATE_DATA = UFix(0, P_REP_TYPE_BITS)
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val P_REP_DOWNGRADE_DATA = UFix(1, P_REP_TYPE_BITS)
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val P_REP_COPY_DATA = UFix(2, P_REP_TYPE_BITS)
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val P_REP_INVALIDATE_ACK = UFix(3, P_REP_TYPE_BITS)
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val P_REP_DOWNGRADE_ACK = UFix(4, P_REP_TYPE_BITS)
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val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
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// external memory interface
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val MEM_TAG_BITS = 4
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@ -117,8 +117,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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mem_req_data = Cat(packet_ram.read(idx), mem_req_data)
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}
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io.mem.xact_init.valid := state === state_mem_req
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io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_WRITE_UNCACHED, X_READ_UNCACHED)
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io.mem.xact_init.bits.has_data := cmd === cmd_writemem
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io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_INIT_WRITE_UNCACHED, X_INIT_READ_UNCACHED)
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io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3)
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io.mem.xact_init_data.valid:= state === state_mem_wdata
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@ -129,8 +129,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
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io.cpu.resp_data := data_mux.io.out
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io.mem.xact_init.valid := (state === s_request)
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io.mem.xact_init.bits.t_type := X_READ_UNCACHED
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io.mem.xact_init.bits.has_data := Bool(false)
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io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
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io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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io.mem.xact_init_data.valid := Bool(false)
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@ -30,8 +30,7 @@ class rocketIPrefetcher extends Component() {
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val ip_mem_resp_val = io.mem.xact_rep.valid && io.mem.xact_rep.bits.tile_xact_id(0)
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io.mem.xact_init.valid := prefetch_miss || (state === s_req_wait)
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io.mem.xact_init.bits.t_type := X_READ_UNCACHED
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io.mem.xact_init.bits.has_data := Bool(false)
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io.mem.xact_init.bits.t_type := X_INIT_READ_UNCACHED
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io.mem.xact_init.bits.tile_xact_id := Mux(prefetch_miss, UFix(0), UFix(1))
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io.mem.xact_init.bits.address := Mux(prefetch_miss, io.icache.xact_init.bits.address, prefetch_addr);
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io.mem.xact_init_data.valid := Bool(false)
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@ -240,8 +240,7 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
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io.meta_req.bits.way_en := way_oh_
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io.mem_req.valid := valid && !requested
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io.mem_req.bits.t_type := Mux(needsWriteback(next_state), X_READ_EXCLUSIVE, X_READ_SHARED)
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io.mem_req.bits.has_data := Bool(false)
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io.mem_req.bits.t_type := Mux(needsWriteback(next_state), X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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io.mem_req.bits.address := Cat(ppn, idx_).toUFix
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io.mem_req.bits.tile_xact_id := Bits(id)
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@ -380,8 +379,7 @@ class WritebackUnit extends Component {
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val wb_req_val = io.req.valid && !valid
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io.refill_req.ready := io.mem_req.ready && !wb_req_val
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io.mem_req.valid := io.refill_req.valid || wb_req_val
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io.mem_req.bits.t_type := Mux(wb_req_val, X_WRITE_UNCACHED, io.refill_req.bits.t_type)
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io.mem_req.bits.has_data := wb_req_val
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io.mem_req.bits.t_type := Mux(wb_req_val, X_INIT_WRITE_UNCACHED, io.refill_req.bits.t_type)
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io.mem_req.bits.address := Mux(wb_req_val, Cat(io.req.bits.ppn, io.req.bits.idx).toUFix, io.refill_req.bits.address)
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io.mem_req.bits.tile_xact_id := Mux(wb_req_val, Bits(NMSHR), io.refill_req.bits.tile_xact_id)
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@ -679,7 +677,7 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
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// refill counter
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val mem_resp_type = io.mem.xact_rep.bits.t_type
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val refill_val = io.mem.xact_rep.valid && (mem_resp_type === X_READ_SHARED || mem_resp_type === X_READ_EXCLUSIVE)
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val refill_val = io.mem.xact_rep.valid && (mem_resp_type === X_REP_READ_SHARED || mem_resp_type === X_REP_READ_EXCLUSIVE)
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val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val rr_count_next = rr_count + UFix(1)
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when (refill_val) { rr_count := rr_count_next }
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